Datasheet

Figure 5. Driver Enable and Disable Times
Figure 4. Enable/Disable Timing Test Load
Figure 3. Driver Propagation Delays
Figure 2. Driver Timing Test Circuit
Figure 1. Driver DC Test Load
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
3V
0V
Y, Z
V
OL
Y, Z
0V
1.5V
1.5V
V
OL
+ 0.25V
V
OH
- 0.25V
2.3V
2.3V
t
ZL(SHDN)
, t
ZL
t
LZ
t
ZH(SHDN)
, t
ZH
t
HZ
DE
S1
S2
OUTPUT
UNDER TEST
V
CC
C
L
R
L
DI
3V
0V
Z
Y
V
O
0V
-V
O
V
O
1.5V
1/2 V
O
1/2 V
O
t
PLH
t
F
t
R
t
PHL
10%
90%
90%
1.5V
10%
V
DIFF
= V (Y) - V (Z)
t
SKEW
= | t
PLH
- t
PHL
|
V
DIFF
f = 1MHz, t
R
3ns, t
F
3ns
DI
DE
3V
Y
V
ID
C
L
C
L
R
DIFF
Z
Y
Z
V
OD
R
R
V
OC
MAX3293–MAX3295 20Mbps, +3.3V, SOT23 RS-485/
RS-422 Transmitters
www.maximintegrated.com
Maxim Integrated │ 5
Test Circuits and Timing Diagrams