Datasheet

MAX31850/MAX31851
Cold-Junction Compensated, 1-Wire
Thermocouple-to-Digital Converters
5Maxim Integrated
Note 2: Limits are 100% production tested at T
A
= +25NC. Limits over the operating temperature range and relevant supply volt-
age range are guaranteed by design and characterization.
Note 3: Limits are 100% production tested at T
A
= +25NC and +85NC. Limits over the operating temperature range and relevant sup-
ply voltage are guaranteed by design and characterization.
Note 4: All voltages are referenced to GND. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 5: The pullup supply voltage specification assumes that the pullup device is ideal, and therefore the high level of the pullup
is equal to V
PU
. To meet the device’s V
IH
specification, the actual supply rail for the strong pullup transistor must include
margin for the voltage drop across the transistor when it is turned on. Thus: V
PU_ACTUAL
= V
PU_IDEAL
+ V
TRANSISTOR
.
Note 6: To guarantee a presence pulse under low-voltage parasite power conditions, V
ILMAX
, may have to be reduced to as low
as 0.5V.
Note 7: Standby current specified up to +70NC.
Note 8: To minimize I
DDS
, DQ should be within the following ranges: V
GND
P V
DQ
P V
GND
+ 0.3V or V
DD
- 0.3V P V
DQ
P V
DD
.
Note 9: Active current refers to supply current during active temperature conversions.
Note 10: DQ is high (high-impedance state with external pullup).
Note 11: Not including cold-junction temperature error or thermocouple nonlinearity.
Note 12: Guaranteed by design. These limits represent six sigma distribution for T
A
= +25NC to +85NC. Outside this temperature
range, these limits are three sigma distribution.
Note 13: Guaranteed by design. These limits represent a three sigma distribution.
Note 14: After minimum V
DD
has been reached during power-up, wait 10ms before initiating temperature conversions.
Note 15: See the 1-Wire Timing Diagrams.
Note 16: Under parasite power, if t
RSTL
> 960Fs, a power-on reset (POR) may occur.
Note 17: Represents the maximum capacitive load that may be applied to the pins and still maintain timing and logic state.
1-Wire TIMING CHARACTERISTICS
(3.0V P V
DD
P 3.6V, T
A
= -40NC to +125NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Time to Strong Pullup On t
SPON
Start Convert T command issued 8 µs
Time Slot t
SLOT
(Note 15) 60 120 µs
Recovery Time t
REC
(Note 15) 1 µs
Write-0 Low Time t
LOW0
(Note 15) 60 120 µs
Write-1 Low Time t
LOW1
(Note 15) 1 15 µs
Read Data Valid t
RDV
(Note 15) 15 µs
Reset Time High t
RSTH
(Note 15) 480 µs
Reset Time Low t
RSTL
(Notes 15, 16) 480 µs
Presence Detect High t
PDHIGH
(Note 15) 15 60 µs
Presence Detect Low t
PDLOW
(Note 15) 60 240 µs
Capacitance: DQ C
IN/OUT
(Note 17) 25 pF
Capacitance: AD0–AD3 C
IN_ADD
(Note 17) 50 pF