Datasheet

MAX31850/MAX31851
Cold-Junction Compensated, 1-Wire
Thermocouple-to-Digital Converters
20Maxim Integrated
and then transmits a presence pulse by pulling the
1-Wire bus low for 60Fs to 240Fs.
Read/Write Time Slots
The bus master writes data to the device during write
time slots and reads data from the device during read
time slots. One bit of data is transmitted over the 1-Wire
bus per time slot.
Write Time Slots
There are two types of write time slots: write-one time
slots and write-zero time slots. The bus master uses a
write-one time slot to write a logic 1 to the slave and a
write-zero time slot to write a logic 0 to the slave. All write
time slots must have a 60Fs (min) duration with a 1Fs
(min) recovery time between individual write slots. Both
types of write time slots are initiated by the master pulling
the 1-Wire bus low (Figure 11).
To generate a write-one time slot, after pulling the 1-Wire
bus low, the bus master must release the 1-Wire bus
within 15Fs. When the bus is released, the 5kI pullup
resistor pulls the bus high. To generate a write-zero time
slot, after pulling the 1-Wire bus low, the bus master must
continue to hold the bus low for the duration of the time
slot (at least 60Fs).
The slave samples the 1-Wire bus during a window that
lasts from 15Fs to 60Fs after the master initiates the write
time slot. If the bus is high during the sampling window,
a 1 is written to the slave. If the line is low, a 0 is written
to the device.
Read Time Slots
The slave can only transmit data to the master when
the master issues read time slots. Therefore, the master
must generate read time slots immediately after issuing
a Read Scratchpad [BEh] command or Read Power
Supply [B4h] command, so that the device can provide
the requested data. In addition, the master can gener-
ate read time slots after issuing a Convert T [44h] com-
mand to verify the operation status as explained in the
MAX31850/MAX31851 Function Commands section.
All read time slots must be 60Fs (min) in duration with a
1Fs (min) recovery time between slots. A read time slot is
initiated by the master device pulling the 1-Wire bus low
for a minimum of 1Fs (t
INIT
) and then releasing the bus
(Figure 11). After the master initiates the read time slot,
the slave begins transmitting a 1 or 0 on bus. The slave
transmits a 1 by leaving the bus high and transmits a 0
by pulling the bus low. When transmitting a 0, the slave
releases the bus by the end of the time slot, and the
pullup resistor pulls the bus back to its high idle state.
Output data from the slave is valid for 15Fs after the fall-
ing edge that initiated the read time slot. Therefore, the
master must release the bus and then sample the bus
state within 15Fs from the start of the slot.
Figure 12 illustrates that the sum of t
INIT
, t
RC
, and the
master sample window must be less than 15Fs for a read
time slot. t
RC
is the rise time due to the resistive and
capacitive characteristics of the bus. Figure 13 shows
that system timing margin is maximized by keeping t
INIT
and t
RC
as short as possible and by locating the master
sample time during read time slots towards the end of
the 15Fs period.
Figure 10. Initialization Timing
V
PU
1-Wire BUS
MASTER Tx RESET PULSE
480µs MINIMUM
MASTER Rx
480µs MINIMUM
MAX31850/MAX31851 Tx PRESENCE PULSE
60µs TO 240µs
MAX31850/MAX31851 WAITS
15µs TO 60µs
GND
BUS MASTER PULLING LOW MAX31850/MAX31851 PULLING LOW RESISTOR PULLUP