Datasheet

MAX3172/MAX3174
+3.3V Multiprotocol Software-Selectable
Cable Terminators and Transceivers
14 ______________________________________________________________________________________
In Figure 11, the MAX3170 and MAX3172/MAX3174 are
placed in V.28 mode. Switches S1 and S2 are opened
on the MAX3172/MAX3174 to place the network in high-
Z mode. Switch S3 is closed on the MAX3170 to enable
the 5kΩ terminating resistor.
V.28 Interface
The V.28 interface is an unbalanced single-ended inter-
face (Figure 12). The V.28 driver generates a minimum
of ±5V across the load impedance between A' and C'.
The V.28 receiver specification calls for input trip points
at ±3V. To aid in rejecting system noise, the MAX3170
V.28 receiver has a typical hysteresis of 0.5V. Also, the
MAX3172/MAX3174 have more tightly specified input
trip points to guarantee fail-safe operation (see Fail-
Safe).
The MAX3172/MAX3174 V.28 receiver provides an
internal 5kΩ termination resistance.
V.10 Interface
The V.10 interface (Figure 12) is an unbalanced single-
ended interface capable of driving a 450Ω load. The
V.10 driver generates a minimum voltage of ±4V
(V
ODO
) across A' and C' when unloaded and a mini-
mum voltage of ±0.9
✕
V
ODO
when loaded with 450Ω.
The V.10 receiver input trip threshold is defined
between +300mV and -300mV with input impedance
characteristics shown in Figure 13.
The MAX3172/MAX3174 V.10 mode receiver has a
threshold between +25mV and +250mV to ensure that
the receiver has proper fail-safe operation (see Fail-
Safe). To aid in rejecting system noise, the MAX3172/
MAX3174 V.10 receiver has a typical hysteresis of
15mV. Switch S3 in Figure 14 is open in V.10 mode to
disable the 5kΩ V.28 termination at the receiver input.
Receiver Glitch Rejection
To allow operation in an unterminated or otherwise
noisy system, the MAX3172 features 10µs of receiver
input glitch rejection. The glitch-rejection circuitry
blocks the reception of high-frequency noise with a bit
period less than 5µs while receiving low-frequency sig-
nals with a bit period greater than 15µs, allowing glitch-
free operation in unterminated systems at up to 64kbps.
Figure 12. Typical V.28 and V.10 Interface
A′
C′
A
C
GENERATOR
UNBALANCED
INTERCONNECTING
CABLE
CABLE
TERMINATION
RECEIVER
LOAD
Figure 11. V.28 Termination and Internal Resistance Networks
R6
10kΩ
R8
5kΩ
R3
127Ω
R2
52Ω
R1
52Ω
A′
B′
C′
A
B
GND
R5
30kΩ
R7
10kΩ
R4
30kΩ
MAX3172
MAX3174
MAX3170
S3
S2
S1
RECEIVER
Figure 13. V.10 Receiver Input Impedance
-3.25mA
3.25mA
-10V
+10V
-3V
+3V
V
Z
I
Z