Datasheet

MAX3140
SCLK’s rising edge. DOUT (MISO) is read into the µP
on SCLK’s rising edge. The first bit (bit 15) of DOUT
transitions on CS’s falling edge, and bits 14–0 transition
on SCLK’s falling edge. Figure 12 shows the detailed
serial timing specifications for the synchronous SPI
port.
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Most operations, such as the
clearing of internal registers, are executed only on CS’s
rising edge. Every time CS goes low, a new 16-bit
stream is expected. Figure 13 shows an example of
using the WRITE CONFIGURATION register.
Table 1 describes the bits located in the WRITE CON-
FIGURATION, READ CONFIGURATION, WRITE DATA,
and READ DATA registers. This table also describes
whether the bit is a read or write bit and what the
power-on reset states (POR) of the bits are. Figure 14
shows an example of parity and word length control.
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
16 ______________________________________________________________________________________
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
t
CSO
t
CL
t
DS
t
DH
t
DV
t
CH
t
DO
t
TR
t
CSH
t
CS1
t
CSS
Figure 12. Detailed Serial Timing Specifications for the Synchronous Port
1
CS
SCLK
DIN
DOUT
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DATA
UPDATED
11 FEN SHDN TM RM PM RAM IR ST PE L B3 B2 B1 B0
RT 00 000 00 0000 000
Figure 13. SPI Interface (Write Configuration)
IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
PE = 1, L = 1
TIME
D0START D1 D2 D3 D4 D5 D6 Pt
STOPSTOP
IDLE
IDLE
PE = 1, L = 0
D0START D1 D2 D3 D4 D5 D6 D7 Pt STOP STOP IDLE
IDLE
PE = 0, L = 1
D0START D1 D2 D3 D4 D5 D6 STOP STOP IDLE
IDLE
PE = 0, L = 0
D0START D1 D2 D3 D4 D5 D6 D7 STOP STOP IDLE
Figure 14. Parity and Word Length Control