Datasheet

SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Baud-Rate Generator
The baud-rate generator determines the rate at which
the transmitter and receiver operate. Bits B3–B0 in the
write configuration register determine the baud-rate
divisor (BRD), which divides the X1 oscillator frequen-
cy. The on-board oscillator operates with either a
1.8432MHz or a 3.6864MHz crystal or is driven at X1
with a 45% to 55% duty-cycle square wave. Table 6
shows baud-rate divisors for given input codes as well
as the baud rate for 1.8432MHz and 3.684MHz crystals.
The generator’s clock is 16-times the baud rate.
Interrupt Sources and Masks
Using the Read Data or Write Data register clears the
interrupt IRQ, assuming the conditions that initiated the
interrupt no longer exist. Table 7 gives the details for
each interrupt source. Figure 6 shows the functional
diagram for the interrupt sources and mask blocks.
Following are two examples of setting up an IRQ for the
MAX3110E/MAX3111E:
Example 1. Set up only the transmit buffer-empty inter-
rupt. Send the 16-bit word below into DIN of the
MAX3110E/MAX3111E using the Write Configuration
register. This 16-bit word configures the MAX3110E/
MAX3111E for 9600bps, 8-bit words, no parity, and one
stop bit with a 1.8432MHz crystal.
binary 1100100000001010
HEX C80A
Example 2. Set up only the data-available (or data-
being-read) interrupt.
Send the 16-bit word below into DIN of the
MAX3110E/MAX3111E using the Write Configuration
register. This 16-bit word configures the MAX3110E/
MAX3111E for 9600bps, 8-bit words, no parity, and one
stop bit with a 1.8432MHz crystal.
binary 1100010000001010
HEX C40A
Receive FIFO
The MAX3110E/MAX3111E contain an 8-word receive
FIFO for data received by the UART to minimize
processor overhead. Using the UART-software shut-
down clears the receive FIFO. Upon power-up, the
receive FIFO is enabled. To disable the receive FIFO,
set the FEN bit high when writing to the Write
Configuration register. To check whether the FIFO is
enabled or disabled, read back the FEN bit using the
Read Configuration.
Table 6. Baud-Rate Selection*
115.2k
230.4k**
BAUD
RATE
(f
OSC
=
3.6864MHz)
BAUD
B3 B2 B1 B0
20001
10 0 0 0**
DIVISION
RATIO
57.6k
115.2k**
BAUD
RATE
(f
OSC
=
1.8432MHz)
28.8k
57.6k
80011
40010
14.4k
28.8k
7200
14.4k
1800
3600
1280111
640110
900
1800
320101
160100
3600
7200
38.4k
76.8k
9600
19.2k
241011
121010
4800
9600
2400
4800
600
1200
3841111
1921110
300
600
961101
481100
1200
2400
61001
31000
19.2k
38.4k
IRQ
N
RM MASK
TM MASK
PM MASK
TRANSITION ON RX
SHUTDOWN
RAM MASK
FRAMING ERROR
SHUTDOWN
RAM MASK
R
S
Q
NEW DATA AVAILABLE
DATA READ
TRANSMIT BUFFER EMPTY
DATA READ
PE = 1 AND RECEIVED
PARITY BIT = 1
PE = 0 OR RECEIVED
PARITY BIT = 0
R
S
Q
R
S
Q
Figure 6. Functional Diagram for Interrupt Sources and Mask
Blocks
*Standard baud rates shown in bold
**Default baud rate
20
Maxim Integrated
MAX3110E/MAX3111E