Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
62 Maxim Integrated
8) The slave asserts an ACK on the data line.
9) The slave sends 8 data bits.
10) The master asserts an ACK on the data line.
11) Repeat 9 and 10 N-2 times.
12) The slave sends the last 8 data bits.
13) The master asserts a NACK on the data line.
14) The master generates a STOP condition.
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX3109 generate ACK bits. To generate
an ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (Figure 26). To generate a NACK, leave
SDA high before the rising edge of the ninth clock pulse
and leave it high for the duration of the ninth clock pulse.
Monitoring for NACK bits allows for detection of unsuc-
cessful data transfers.
Applications Information
Startup and Initialization
The MAX3109 can be initialized following power-up,
a hardware reset, or a software reset as shown in
Figure 27. To verify that the MAX3109 is ready for opera-
tion after a power-up or reset.
Repeatedly read a known register until the expected
contents are returned. The MAX3109 is ready for opera-
tion after approximately 200Fs.
Figure 26. Acknowledge
Figure 27. Startup and Initialization Flowchart
NOT-ACKNOWLEDGE
ACKNOWLEDGE
12 89
SDA
SCL
S
POWER-UP/
RST INPUT PULLED HIGH
IS
DIVLSB READ
SUCCESSFULLY?
Y
N
CONFIGURE
CLOCKING
CONFIGURE
MODES
CONFIGURE
FIFO CONTROL
CONFIGURE
FLOW CONTROL
CONFIGURE
GPIOs
START
COMMUNICATION
ENABLE
INTERRUPTS