Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
61Maxim Integrated
Single-Byte Read
In this operation, the master sends an address plus two
data bytes and receives one data byte from the slave
device (Figure 24). The following procedure describes
the single-byte read operation:
1) The master sends a START condition.
2) The master sends the 7-bit slave address plus a write
bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The active slave asserts an ACK on the data line only
if the address is valid (NACK if not).
6) The master sends a repeated START condition.
7) The master sends the 7-bit slave address plus a read
bit (high).
8) The addressed slave asserts an ACK on the data line.
9) The slave sends 8 data bits.
10) The master asserts a NACK on the data line.
11) The master generates a STOP condition.
Burst Read
In this operation, the master sends an address plus
two data bytes and receives multiple data bytes from
the slave device (Figure 25). The following procedure
describes the burst byte read operation:
1) The master sends a START condition.
2) The master sends the 7-bit slave address plus a write
bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the
address is valid (NACK if not).
6) The master sends a repeated START condition.
7) The master sends the 7-bit slave address plus a read
bit (high).
Figure 24. Read Byte Sequence
Figure 25. Burst Read Sequence
S
Sr
DEVICE SLAVE ADDRESS - W A
DEVICE SLAVE ADDRESS - R
READ SINGLE BYTE
A
REGISTER ADDRESS A
8 DATA BITS NA
FROM MASTER TO STAVE FROM SLAVE TO MASTER
P
S
Sr
DEVICE SLAVE ADDRESS - W A
DEVICE SLAVE ADDRESS - R
BURST READ
A
REGISTER ADDRESS A
8 DATA BITS - 1A
A 8 DATA BITS - 38 DATA BITS -
2A
8 DATA BITS - NNA
FROM MASTER TO STAVE FROM SLAVE TO MASTER
P