Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
59Maxim Integrated
bus, or a repeated START condition (Sr) to communi-
cate to another I
2
C slave. See Figure 21.
Slave Address
The MAX3109 includes a configurable 7-bit I
2
C slave
address, allowing up to 16 MAX3109 devices to share
the same I
2
C bus. The address is defined by connect-
ing the MOSI/A1 and CS/A0 inputs to DGND, V
L
, SCL,
or SDA (Table 5). Set the R/W bit high to configure the
MAX3109 to read mode. Set the R/W bit low to config-
ure the MAX3109 to write mode. The address is the
first byte of information sent to the MAX3109 after the
START condition.
Bit Transfer
One data bit is transferred on the rising edge of each
SCL clock cycle. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes
in SDA while SCL is high and stable are considered
control signals (see the START, STOP, and Repeated
START Conditions section). Both SDA and SCL remain
high when the bus is not active.
Figure 21. I
2
C START, STOP, and Repeated START Conditions
Table 8. I
2
C Address Map
SCL
SDA
SS
rP
MOSI/A1
CS/A0
UART0 UART1
WRITE READ WRITE READ
DGND DGND 0xD8 0xD9 0xB8 0xB9
DGND V
L
0xC2 0xC3 0xA2 0xA3
DGND SCL 0xC4 0xC5 0xA4 0xA5
DGND SDA 0xC6 0xC7 0xA6 0xA7
V
L
DGND 0xC8 0xC9 0xA8 0xA9
V
L
V
L
0xCA 0xCB 0xAA 0xAB
V
L
SCL 0xCC 0xCD 0xAC 0xAD
V
L
SDA 0xCE 0xCF 0xAE 0xAF
SCL DGND 0xD0 0xD1 0xB0 0xB1
SCL V
L
0xD2 0xD3 0xB2 0xB3
SCL SCL 0xD4 0xD5 0xB4 0xB5
SCL SDA 0xD6 0xD7 0xB6 0xB7
SDA DGND 0xC0 0xC1 0xA0 0xA1
SDA V
L
0xDA 0xDB 0xBA 0xBB
SDA SCL 0xDC 0xDD 0xBC 0xBD
SDA SDA 0xDE 0xDF 0xBE 0xBF