Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
58 Maxim Integrated
SPI Burst Access
Burst access allows writing and reading multiple data
bytes in one block by defining only the initial register
address in the SPI command byte. Multiple characters
can be loaded into the TxFIFO by using the THR (0x00)
as the initial burst write address. Similarly, multiple
characters can be read out of the RxFIFO by using the
RHR (0x00) as the SPI’s burst read address. If the SPI
burst address is different from 0x00, the MAX3109 auto-
matically increments the register address after each SPI
data byte. Efficient programming of multiple consecutive
registers is thus possible. The chip-select input, CS/A0,
must be held low during the whole cycle. The SCLK/SCL
clock continues clocking throughout the burst access
cycle. The burst cycle ends when the SPI master pulls
CS/A0 high.
For example, writing 128 bytes into the TxFIFO can be
achieved by a burst write access using the following
sequence:
1) Pull CS/A0 low.
2) Send SPI write command to address 0x00.
3) Send 128 bytes.
4) Release CS/A0.
This takes a total of (1 + 128) x 8 clock cycles.
Fast Read Cycle
The two UART interrupts on the MAX3109 share the
single IRQ output. When operating in interrupt-based
mode, the microcontroller needs to locate the source
of the interrupt (i.e., which of the UARTs generated the
interrupt) and clear the interrupt.
In order to locate the source of an interrupt more quickly,
the MAX3109 implements the SPI fast read cycle. This
means that the microcontroller can determine which
UART is the source of the interrupt (UART0 or UART1)
using only 8 clock cycles (Figure 20). The U bit is
ignored during the fast read cycle.
I
2
C Interface
The MAX3109 contains an I
2
C-compatible interface for
data communication with a host processor (SCL and
SDA). The interface supports a clock frequency of up
to 1MHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
START, STOP, and Repeated START Conditions
When writing to the MAX3109 using I
2
C, the master
sends a START condition (S) followed by the MAX3109
I
2
C address. After the address, the master sends
the register address of the register that is to be pro-
grammed. The master then ends communication by
issuing a STOP condition (P) to relinquish control of the
Figure 20. SPI Fast Read Cycle
MOSI
Ax = REGISTER ADDRESS
SCLK
CS
MISO
0
HIGH-Z
R
U
A4
A3 A2
A1
A0
00IRQ1 IRQ0