Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
57Maxim Integrated
Serial Controller Interface
The MAX3109 can be controlled through I
2
C or SPI as
defined by the logic on SPI/I2C. See the Pin Description
for further details.
SPI Interface
The SPI supports both single-cycle and burst read/write
access. The SPI master must generate clock and data
signals in SPI MODE0 (i.e., with clock polarity CPOL = 0
and clock phase CPHA = 0).
Each of the two UARTs is addressed using 1 bit (U) in the
command byte (Table 7).
To access the registers with addresses 0x20 or higher in
SPI mode, enable extended register map access. See the
GloblComnd register description for more information.
SPI Single-Cycle Access
Before a specific UART has been addressed, both
UARTs could attempt to drive MISO. To avoid this con-
tention, the MISO line is held in high impedance during a
write cycle (Figure 18).
During a read cycle, MISO is high impedance for the first
four clock cycles of the command byte. Once the SPI
address has been properly decoded, the addressed SPI
drives the MISO line (Figure 19).
Figure 18. SPI Write Cycle
Figure 19. SPI Ready Cycle
Table 7. SPI Command Byte Configuration
Ax = Register address.
HIGH-Z
Ax = REGISTER ADDRESS
Dx = 8-BIT REGISTER CONTENTS
CS
SCLK
MOSI
MISO
W0
U
A4 A3
A2 A1 A0 D7
D6 D5 D4
D3 D2 D1 D0
HIGH-Z
Ax = REGISTER ADDRESS
Dx = 8-BIT REGISTER CONTENTS
SCLK
MOSI
MISO
R
0
U
A4 A3
A2 A1 A0
CS
00IRQ1 IRQ0 D7 D6 D5 D4 D3 D2 D1 D0
SPI COMMAND BYTE
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
W/R
0 U A4 A3 A2 A1 A0