Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
56 Maxim Integrated
Timer Register 1 (TIMER1)
The TIMER1 and TIMER2 register contents can be used to generate a low-frequency clock signal on a GPIO_ output.
The low-frequency clock is a divided replica of the fractional baud-rate generator output. If TIMER1 and TIMER2 are
both 0x00, the low-frequency clock is off.
Bits 7–0: Timerx
The TIMER1[7:0] bits are the 8 LSBs of the 15-bit timer divisor. See the TIMER2 register description.
Timer Register 2 (TIMER2)
The TIMER1 and TIMER2 register contents can be used to generate a low-frequency clock signal on a GPIO_ output.
The low-frequency clock is a divided replica of the fractional baud-rate generator output. If TIMER1 and TIMER2 are
both 0x00, the low-frequency clock is off.
Bit 7: TmrToGPIO
Set the TmrToGPIO bit high to enable clock generation at a GPIO output. The clock signal is routed to GPIO1 for UART0
and GPIO5 for UART1. The output clock has a 50% duty cycle.
Bits 6–0: Timerx
The TIMER2[6:0] bits are the 7 MSBs of the 15-bit timer divisor. The clock frequency is calculated using the following
formula:
f
TIMER_CLK
= UARTClk/(1024 x Timerx)
where UARTClk is the fractional baud-rate generator output (i.e., 16 x Baud Rate).
Revision Identification Register (RevID)
Bits 7–0: Bitx
The RevID register indicates the revision number of the MAX3109 silicon starting with 0xC0. This can be used during
software development as a known reference.
ADDRESS: 0x24
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
TmrToGPIO Timer14 Timer13 Timer12 Timer11 Timer10 Timer9 Timer8
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x25
MODE: R
BIT 7 6 5 4 3 2 1 0
NAME
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RESET
1 1 0 0 0 0 1 0
ADDRESS: 0x23
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
Timer7 Timer6 Timer5 Timer4 Timer3 Timer2 Timer1 Timer0
RESET
0 0 0 0 0 0 0 0