Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
55Maxim Integrated
Synchronization Delay Register 1 (SynchDelay1)
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelayx
The SDelayx bits are the 8 LSBs of the delay between when the UART receives an assigned transmitter trigger com-
mand and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate).
The maximum delay is 65,535 bit intervals.
For example, given a baud rate of 230.4kbps, the bit time is 4.34Fs, so the maximum delay is 284ms.
Synchronization Delay Register 2 (SynchDelay2)
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelayx
The SDelayx bits are the 8 MSBs of the delay between when the UART receives an assigned transmitter trigger com-
mand and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate).
The maximum delay is 65,535 bit intervals.
For example, given a baud rate of 230.4kbps, the bit time is 4.34Fs, so the maximum delay is 284ms.
ADDRESS: 0x21
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
SDelay7 SDelay6 SDelay5 SDelay4 SDelay3 SDelay2 SDelay1 SDelay0
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x22
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
SDelay15 SDelay14 SDelay13 SDelay12 SDelay11 SDelay10 SDelay9 SDelay8
RESET
0 0 0 0 0 0 0 0