Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
52 Maxim Integrated
Global IRQ Register (GlobalIRQ)
Bit 7–2: No Function
Bits 1-0: IRQx
The MAX3109 has a single IRQ output. The GlobalIRQ register bits report which of the UARTs have an interrupt pend-
ing, as enabled in the ISRIntEn registers.
The GlobalIRQ register can be read in two ways: either by reading register 0x1F of any of the two UARTs or by sam-
pling the two bits sent to the master on MISO during the command byte of a read cycle (full-duplex SPI) (see the Fast
Read Cycle section for more information).
The IRQx bits are set low when the associated UARTs have an IRQ interrupt pending. The IRQx bits are cleared high
when the associated UART interrupt is cleared. UART interrupts are cleared by reading the UART ISR register.
ADDRESS: 0x1F
MODE: R
BIT 7 6 5 4 3 2 1 0
NAME
— — — — — —
IRQ1 IRQ0
RESET
0 0 0 0 0 0 1 1