Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
51Maxim Integrated
Baud-Rate Generator MSB Divisor Register (DIVMSB)
DIVLSB and DIVMSB define the baud-rate generator integer divisor. The minimum value for DIVLSB is 1. See the
Fractional Baud-Rate Generator section for more information.
Bits 7–0: Divx
The Divx bits are the eight MSBs of the integer divisor portion (DIV) of the baud-rate generator.
Clock Source Register (CLKSource)
Bit 7: CLKtoRTS
Set the CLKtoRTS bit high to route the baud-rate generator (16x baud rate) output clock to RTS_. The RTS_ clock fre-
quency is a factor of 16x, 8x, or 4x of the baud rate in 1x, 2x, and 4x rate modes, respectively.
Bits 6, 5, 4, and 0: No Function
Bit 3: PLLBypass
Set the PLLBypass bit high to bypass the internal PLL and predivider.
Bit 2: PLLEn
Set the PLLEn bit high to enable the internal PLL. Set PLLEn low to disable the internal PLL.
Bit 1: CrystalEn
Set the CrystalEn bit high to enable the crystal oscillator. When using an external clock source at XIN, set CrystalEn low.
ADDRESS: 0x1E
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
CLKtoRTS — — — PLLBypass PLLEn CrystalEn —
RESET
0 0 0 1 1 0 0 0
ADDRESS: 0x1D
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
Div15 Div14 Div13 Div12 Div11 Div10 Div9 Div8
RESET
0 0 0 0 0 0 0 0