Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
50 Maxim Integrated
Baud-Rate Generator Configuration Register (BRGConfig)
Bits 7 and 6: No Function
Bit 5: 4xMode
Set the 4xMode bit high to quadruple the regular (16x sampling) baud rate. Set the 2xMode bit low when 4xMode is
enabled. See the 2x and 4x Rate Modes section for more information.
Bit 4: 2xMode
Set the 2xMode bit high to double the regular (16x sampling) baud rate. Set the 4xMode bit low when 2xMode is
enabled. See the 2x and 4x Rate Modes section for more information.
Bits 3–0: FRACTx
The FRACTx bits are the fractional portion of the baud-rate generator divisor. Set FRACTx to 0000b if not used. See the
Fractional Baud-Rate Generator section for calculations of how to set this value to select the baud rate.
Baud-Rate Generator LSB Divisor Register (DIVLSB)
DIVLSB and DIVMSB define the baud-rate generator integer divisor. The minimum value for DIVLSB is 1. See the
Fractional Baud-Rate Generator section for more information.
Bits 7–0: Divx
The Divx bits are the eight LSBs of the integer divisor portion (DIV) of the baud-rate generator.
ADDRESS: 0x1B
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
— — 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x1C
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
Div7 Div6 Div5 Div4 Div3 Div2 Div1 Div0
RESET
0 0 0 0 0 0 0 1