Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
49Maxim Integrated
Table 4. PLLFactorx Selection Guide
Figure 17. PLL Signal Path
PLL Configuration Register (PLLConfig)
Bits 7–6: PLLFactorx
The PLLFactorx bits allow programming the PLL multiplication factor. The input and output frequencies of the PLL must
be limited to the ranges shown in Table 4. Enable the PLL in CLKSource[2].
Bits 5–0: PreDivx
The PreDivx bits allow programming of the divisor in the PLL’s predivider. The divisor must be chosen such that the
output frequency of the predivider, which is the PLL’s input frequency, is limited to the ranges shown in Table 4. The
PLL input frequency is calculated as:
f
PLLIN
= f
CLK
/PreDiv
where f
CLK
is the input frequency of the crystal oscillator or external clock source (Figure 17), and PreDiv is an integer
in the range of 1 to 63.
PREDIVIDER
f
CLK
PLL
f
PLLIN
f
REF
FRACTIONAL
BAUD-RATE
GENERATOR
ADDRESS: 0x1A
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0
RESET
0 0 0 0 0 0 0 1
PLLFactor1 PLLFactor0
MULTIPLICATION
FACTOR
f
PLLIN
f
REF
MIN MAX MIN MAX
0 0 6 500kHz 800kHz 3MHz 4.8MHz
0 1 48 850kHz 1.2MHz 40.8MHz 56MHz
1 0 96 425kHz 1MHz 40.8MHz 96MHz
1 1 144 390kHz 667kHz 56MHz 96MHz