Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
37Maxim Integrated
Status Interrupt Register (STSInt)
Bit 7: TxEmptyInt
The TxEmptyInt interrupt is generated when both the TxFIFO is empty and the last character has completed transmis-
sion. TxEmptyInt is cleared after STSInt is read. TxEmptyInt generates an interrupt in ISR[2] if enabled by STSIntEn[7].
Bit 6: SleepInt
The SleepInt status bit is generated when the MAX3109 enters sleep mode. SleepInt is cleared when the UART exits
sleep mode. This status bit is also cleared when the UART clock is disabled and is not cleared by reading STSInt.
SleepInt generates an interrupt in ISR[2] if enabled by STSIntEn[6].
Bit 5: ClkReady
The ClkReady status bit is generated when the clock, the predivider, and the PLL have settled, signifying that the
MAX3109 is ready for data communication. The ClkReady bit only works with the crystal oscillator. It does not work
with external clocking through XIN.
ClkReady is cleared when the clock is disabled and is not cleared after STSInt is read. ClkReady generates an inter-
rupt in ISR[2] if enabled by STSIntEn[5].
Bit 4: No Function
Bits 3–0: GPIxInt
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7.
For example, for UART1: GP0OD configures GPIO4, GP1OD configures GPIO5, GP2OD configures GPIO6 and GP3OD
configures GPIO7.
The GPIxInt interrupts are generated when a change of logic state occurs on the associated GPIO input. The GPIxInt
interrupts are cleared after STSInt is read. The GPIxInt interrupts generate an interrupt in ISR[2] if enabled by the cor-
responding bits in STSIntEn[3:0].
ADDRESS: 0x08
MODE: R/COR
BIT 7 6 5 4 3 2 1 0
NAME
TxEmptyInt SleepInt ClkReady — GPI3Int GPI2Int GPI1Int GPI0Int
RESET
0 0 0 0 0 0 0 0