Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
36 Maxim Integrated
STS Interrupt Enable Register (STSIntEn)
STSIntEn allows routing of STSInt interrupts to ISR[2]. The STSIntEn bits only influence the ISR[2]: STSInt bit and do
not have any effect on the STSInt contents or behavior, with the exception of the GPIxIntEn interrupt enable bits, which
control the generation of the STSInt.
Bit 7: TxEmptyIntEn
Set the TxEmptyIntEn bit high to enable routing the STSInt[7]: TxEmptyInt interrupt to ISR[2]. If TxEmptyIntEn is set
low, TxEmptyInt is not routed to ISR[2].
Bit 6: SleepIntEn
Set the SleepIntEn bit high to enable routing the STSInt[6]: SleepInt interrupt to ISR[2]. If SleepIntEn is set low, SleepInt
is not routed to ISR[2].
Bit 5: ClkRdyIntEn
Set the ClkRdyIntEn bit high to enable routing the STSInt[6]: ClkReady interrupt to ISR[2]. If ClkRdyIntEn is set low,
ClkReady is not routed to ISR[2].
Bit 4: No Function
Bits 3–0: GPIxIntEn
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7.
For example, for UART1: GP0OD configures GPIO4, GP1OD configures GPIO5, GP2OD configures GPIO6 and
GP3OD configures GPIO7.
Set the GPIxIntEn bits high to enable generating the STSInt[3:0]: GPIxInt interrupts. If any of the GPIxIntEn bits are set
low, the associated GPIxInt interrupts are not generated.
ADDRESS: 0x07
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
TxEmptyIntEn SleepIntEn ClkRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn
RESET
0 0 0 0 0 0 0 0