Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
32 Maxim Integrated
Line Status Interrupt Enable Register (LSRIntEn)
LSRIntEn allows routing of LSR interrupts to ISR[0]. The LSRIntEn bits only influence the ISR[0]: LSRErrInt bit and do
not have any effect on the LSR contents or behavior. Bits 5 to 0 of the LSRIntEn register operate on a corresponding
LSR bit, while bits 7 and 6 are not used.
Bits 7 and 6: No Function
Bit 5: NoiseIntEn
Set the NoiseIntEn bit high to enable routing the LSR[5]: RxNoise interrupt to ISR[0]. If NoiseIntEn is set low, RxNoise
is not routed to ISR[0].
Bit 4: RBreakIEn
Set the RBreakIEn bit high to enable routing the LSR[4]: RxBreak interrupt to ISR[0]. If RBreakIEn is set low, RxBreak
is not routed to ISR[0].
Bit 3: FrameErrIEn
Set the FrameErrIEn bit high to enable routing the LSR[3]: FrameErr interrupt to ISR[0]. If FrameErrIEn is set low,
FrameErr is not routed to ISR[0].
Bit 2: ParityIEn
Set the ParityIEn bit high to enable routing the LSR[2]: RxParityErr interrupt to ISR[0]. If ParityIEn is set low, RxParityErr
is not routed to ISR[0].
Bit 1: ROverrIEn
Set the ROverrIEn bit high to enable routing the LSR[1]: RxOverrun interrupt to ISR[0]. If ROverrIEn is set low,
RxOverrun is not routed to ISR[0].
Bit 0: RTimoutIEn
Set the RTimoutIEn bit high to enable routing the LSR[0]: RTimeout interrupt to ISR[0]. If RTimoutIEn is set low,
RTimeout is not routed to ISR[0].
ADDRESS: 0x03
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
— — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn
RESET
0 0 0 0 0 0 0 0