Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
29Maxim Integrated
Detailed Register Descriptions
The MAX3109 has 8-bit-wide registers. When using SPI control, the extended register location (0x20 through 0x25) can
only be accessed by first enabling extended read/writing through GloblComnd. Each UART has an exclusive set of
registers. Select a UART to write to by setting the U bit of the command byte in SPI mode or the unique I
2
C address
in I
2
C mode (see the Serial Controller Interface section for more information).
Receive Hold Register (RHR)
Bits 7–0: RDatax
The RHR is the bottom of the receive FIFO and is the register used for reading data out of the receive FIFO. It contains
the oldest (first received) character in the receive FIFO. RHR[0] is the LSB of the character received at the RX_ input.
It is the first data bit of the serial-data word received by the receiver. Reading RHR removes the read word from the
receive FIFO, clearing space for more data to be received.
Transmit Hold Register (THR)
Bits 7–0: TDatax
The THR is the register that the host controller writes data to for subsequent UART transmission. This data is depos-
ited in the transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out,
immediately after the START bit.
ADDRESS: 0x00
MODE: R
BIT 7 6 5 4 3 2 1 0
NAME
RData7 RData6 RData5 RData4 RData3 RData2 RData1 RData0
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x00
MODE: W
BIT 7 6 5 4 3 2 1 0
NAME
TData7 TData6 TData5 TData4 TData3 TData2 TData1 TData0
RESET
0 0 0 0 0 0 0 0