Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
28 Maxim Integrated
Register Map
(Note: All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.)
1
Denotes nonread/write mode: RHR = R, THR = W, ISR = COR, LSR = R, SpclCharInt = COR, STSInt = R/COR, TxFIFOLvl
= R,
RxFIFOLvl = R, GlobalIRQ = R, GloblComnd = W, RevID = R.
2
Denotes nonzero default reset value: ISR = 0x60, LCR = 0x05, FIFOTrgLvl = 0xFF, PLLConfig = 0x01, DIVLSB = 0x01,
CLKSource = 0x18, GlobalIRQ = 0x03, RevID = 0xC1.
3
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7.
4
Denotes a register that can only be programmed by accessing UART0.
5
Denotes a register that can only be directly addressed in I
2
C mode. Use extended addressing when operating in SPI mode.
REGISTER ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FIFO DATA
RHR
1
0x00 RData7 RData6 RData5 RData4 RData3 RData2 RData1 RData0
THR
1
0x00 TData7 TData6 TData5 TData4 TData3 TData2 TData1 TData0
INTERRUPTS
IRQEn 0x01 CTSIEn RxEmtyIEn TFifoEmtyIEn TxTrgIEn RxTrgIEn STSIEn SpChrIEn LSRErrIEn
ISR
1, 2
0x02 CTSInt RxEmptyInt TFifoEmptyInt TxTrgInt RxTrigInt STSInt SpCharInt LSRErrInt
LSRIntEn 0x03 — — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn
LSR
1, 2
0x04
CTSbit
— RxNoise RxBreak FrameErr RxParityErr RxOverrun RTimeout
SpclChrIntEn 0x05 — — MltDrpIntEn BREAKIntEn XOFF2IntEn XOFF1IntEn XON2IntEn XON1IntEn
SpclCharInt
1
0x06 — — MultiDropInt BREAKInt XOFF2Int XOFF1Int XON2Int XON1Int
STSIntEn
3
0x07 TxEmptyIntEn SleepIntEn ClkRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn
STSInt
1, 2, 3
0x08 TxEmptyInt SleepInt ClkReady — GPI3Int GPI2Int GPI1Int GPI0Int
UART MODES
MODE1 0x09 — AutoSleep ForcedSleep TrnscvCtrl RTSHiZ TxHiZ TxDisabl RxDisabl
MODE2 0x0A EchoSuprs
MultiDrop Loopback SpecialChr RFifoEmptyInv RxTrgInv FIFORst RST
LCR
2
0x0B
RTSbit
TxBreak ForceParity EvenParity ParityEn StopBits Length1 Length0
RxTimeOut 0x0C TimOut7 TimOut6 TimOut5 TimOut4 TimOut3 TimOut2 TimOut1 TimOut0
HDplxDelay 0x0D Setup3 Setup2 Setup1 Setup0 Hold3 Hold2 Hold1 Hold0
IrDA 0x0E — — TxInv RxInv MIR — SIR IrDAEn
FIFOs CONTROL
FlowLvl 0x0F Resume3 Resume2 Resume1 Resume0 Halt3 Halt2 Halt1 Halt0
FIFOTrgLvl
2
0x10 RxTrig3 RxTrig2 RxTrig1 RxTrig0 TxTrig3 TxTrig2 TxTrig1 TxTrig0
TxFIFOLvl
1
0x11 TxFL7 TxFL6 TxFL5 TxFL4 TxFL3 TxFL2 TxFL1 TxFL0
RxFIFOLvl
1
0x12 RxFL7 RxFL6 RxFL5 RxFL4 RxFL3 RxFL2 RxFL1 RxFL0
FLOW CONTROL
FlowCtrl 0x13 SwFlow3 SwFlow2 SwFlow1 SwFlow0 SwFlowEn GPIAddr AutoCTS AutoRTS
XON1 0x14 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XON2 0x15 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XOFF1 0x16 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XOFF2 0x17 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GPIOs
GPIOConfg
3
0x18 GP3OD GP2OD GP1OD GP0OD GP3Out GP2Out GP1Out GP0Out
GPIOData
3
0x19 GPI3Dat GPI2Dat GPI1Dat GPI0Dat GPO3Dat GPO2Dat GPO1Dat GPO0Dat
CLOCK CONFIGURATION
PLLConfig
2, 4
0x1A PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0
BRGConfig 0x1B — — 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0
DIVLSB
2
0x1C Div7 Div6 Div5 Div4 Div3 Div2 Div1 Div0
DIVMSB 0x1D Div15 Div14 Div13 Div12 Div11 Div10 Div9 Div8
CLKSource
2, 4
0x1E CLKtoRTS — — — PLLBypass PLLEn CystalEn —
GLOBAL REGISTERS
GlobalIRQ
1, 2
0x1F 0 0 0 0 0 0
IRQ1 IRQ0
GloblComnd
1
0x1F GlbCom7 GlbCom6 GlbCom5 GlbCom4 GlbCom3 GlbCom2 GlbCom1 GlbCom0
SYNCHRONIZATION
TxSynch
5
0x20 CLKtoGPIO TxAutoDis TrigDelay SynchEn TrigSel3 TrigSel2 TrigSel1 TrigSel0
SynchDelay1
5
0x21 SDelay7 SDelay6 SDelay5 SDelay4 SDelay3 SDelay2 SDelay1 SDelay0
SynchDelay2
5
0x22 SDelay15 SDelay14 SDelay13 SDelay12 SDelay11 SDelay10 SDelay9 SDelay8
TIMER REGISTERS
TIMER1
5
0x23 Timer7 Timer6 Timer5 Timer4 Timer3 Timer2 Timer1 Timer0
TIMER2
5
0x24 TmrToGPIO Timer14 Timer13 Timer12 Timer11 Timer10 Timer9 Timer8
REVISION
RevID
1, 2, 5
0x25 1 1 0 0 0 0 1 0