Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
18 Maxim Integrated
The following three error conditions are checked for each
received word: parity error, frame error, and noise on the
line. Parity errors are detected by calculating either even
or odd parity of the received word as programmed by
register settings. Framing errors are detected when the
received data frame does not match the expected frame
format in length. Line noise is detected by checking the
logical congruency of the three samples taken of each
bit (Figure 6).
The receiver can be turned off by setting the MODE1[0]:
RxDisabl bit high. After this bit is set high, the MAX3109
turns the receiver off immediately following the current
word and does not receive any further data.
The RX_ input logic can be inverted by setting the
IrDA[4]: RxInv bit high. Unless otherwise noted, all
receiver logic described in this data sheet assumes that
RxInv is set low.
Line Noise Indication
When operating in standard or 2x (i.e., not 4x) rate mode,
the MAX3109 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples per received bit have differing logic
levels, then noise on the transmission line has affected
the received data and it is considered to be noisy. This
noise indication is reflected in the LSR[5]: RxNoise bit for
each received byte. Parity errors are another indication
of noise, but are not as sensitive.
Figure 5. Receive FIFO
Figure 6. Midbit Sampling
RECEIVE FIFO
FIFOTrgLvl[7:4]
TRIGGER
ISR[3]
WORD ERROR 128
RxFIFOLvl
4
3
2
1
TIMEOUT
EMPTY
ERRORS
OVERRUN
LSR[1]
RECEIVED
DATA
RHR
RECEIVER RX_
I
2
C/SPI INTERFACE
LSR[0]
ISR[6]
LSR[5:2]
CURRENT FILL LEVEL
1
RX_
BAUD
BLOCK
23456789
ONE BIT PERIOD
10 11
MAJORITY
CENTER
SAMPLER
12 13 14 15 16
A