Datasheet
Dual Serial UART with 128-Word FIFOs
MAX3109
14 Maxim Integrated
Pin Configuration
Pin Description
TQFN
(5mm × 5mm)
TOP VIEW
29
30
28
27
12
11
13
MISO/SDA
GPIO7
CS/A0
MOSI/A1
IRQ
14
RST
GPIO2
RTS0
RX1
GPIO3
RX0
TX0
12
GPIO6
4567
2324 22 20 19 18
AGND
LDOEN
GPIO5
GPIO1
GPIO4
GPIO0
SCLK/SCL
RTS1
3
21
31
10
V
18
DGND
32
9
V
CC
+
SPI/I2C
XOUT
26
15
CTS0
XIN
25
16
CTS1
V
L
TX1
8
17
V
EXT
*EP
*CONNECT EP TO AGND.
MAX3109
PIN NAME FUNCTION
1 RST
Active-Low Reset Input. Drive RST low to force all of the UARTs into hardware reset mode. Driving RST
low also enables low-power shutdown mode. When RST is low, the internal V18 LDO is switched off,
even if the LDOEN input is kept high.
2 MISO/SDA
Serial-Data Output. When SPI/I2C is high, MISO/SDA functions as the SPI master input-slave output
(MISO). When SPI/I2C is low, MISO/SDA functions as the SDA, I
2
C serial-data input/output. MISO/SDA is
high impedance when RST is driven low or when the externally supplied V18 is powered off.
3 SCLK/SCL
Serial-Clock Input. When SPI/I2C is high, SCLK/SCL functions as the SCLK SPI serial-clock input (up to
26MHz). When SPI/I2C is low, SCLK/SCL functions as the SCL, I
2
C serial-clock input (up to 1MHz in fast
mode plus).
4 GPIO7
General-Purpose Input/Output 7. GPIO7 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO7 has a weak pulldown resistor to DGND when
configured as an input.
5 CS/A0
Active-Low Chip-Select and Address 0 Input. When SPI/I2C is high, CS/A0 functions as the CS, SPI
active-low chip-select. When SPI/I2C is low, CS/A0 functions as the A0 I
2
C device address programming
input. Connect CS/A0 to DGND, V
L
, SCL, or SDA when SPI/I2C is low.
6 MOSI/A1
Serial-Data Input and Address 1 Input. When SPI/I2C is high, MOSI/A1 functions as the SPI master
output-slave input (MOSI). When SPI/I2C is low, MOSI/A1 functions as the A1 I
2
C device address
programming input. Connect MOSI/A1 to DGND, V
L
, SCL, or SDA when SPI/I2C is low.
7 IRQ
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending. IRQ is high
impedance when RST is driven low.