Datasheet

SPI/I
2
C UART with 128-Word FIFOs
MAX3107
46 Maxim Integrated
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data
line.
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the
address is valid (NACK if not).
6) The master sends 8 bits of data.
7) The slave asserts an ACK on the data line.
8) Repeat steps 6 and 7 N - 1 times.
9) The master generates a STOP condition.
Single-Byte Read
With this operation the master sends an address and
receives 1 or 2 data bytes from the slave device
(Figure 20). The read byte procedure is as follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The active slave asserts an ACK on the data line only
if the address is valid (NACK if not).
6) The master sends a repeated START (Sr).
7) The master sends the 7-bit slave ID plus a read bit (high).
Figure 19. Burst Write Sequence
Figure 20. Read Byte Sequence
Figure 18. Write Byte Sequence
S DEVICE SLAVE ADDRESS - W A
8 DATA BITS - 1
BURST WRITE
A
REGISTER ADDRESS A
8 DATA BITS - N A
8 DATA BITS - 2 A
FROM MASTER TO STAVE FROM SLAVE TO MASTER
P
S
Sr
DEVICE SLAVE ADDRESS - W A
DEVICE SLAVE ADDRESS - R
READ SINGLE BYTE
A
REGISTER ADDRESS A
8 DATA BITS NA
FROM MASTER TO STAVE FROM SLAVE TO MASTER
P
S
P
DEVICE SLAVE ADDRESS - W A
8 DATA BITS
FROM MASTER TO STAVE
WRITE SINGLE BYTE
FROM SLAVE TO MASTER
A
REGISTER ADDRESS A