Datasheet

SPI/I
2
C UART with 128-Word FIFOs
MAX3107
45Maxim Integrated
START, STOP, and Repeated START Conditions
When writing to the MAX3107 using I
2
C, the master
sends a START condition (S) followed by the MAX3107
I
2
C address. After the address, the master sends
the register address of the register that is to be pro-
grammed. The master then ends communication by
issuing a STOP condition (P) to relinquish control of the
bus, or a repeated START condition (Sr) to communicate
to another I
2
C slave. See Figure 17.
Slave Address
The MAX3107 includes a 7-bit slave address. The first 5
bits (MSBs) of the slave address are factory-programmed
and always 01011. These slave addresses are unique
device IDs. Connect A1, A0 to ground or V
L
to set the
I
2
C slave address (Table 5). The address is defined as
the 7 MSBs followed by the read/write bit. Set the read/
write bit to 1 to configure the MAX3107 to read mode. Set
the read/write bit to 0 to configure the MAX3107 to write
mode. The address is the first byte of information sent to
the MAX3107 after the START condition.
Bit Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the START, STOP, and Repeated START Conditions
section). Both SDA and SCL remain high when the bus
is not active.
Single-Byte Write
With this operation the master sends an address and 1
or 2 data bytes to the slave device (Figure 18). The write
byte procedure is as follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The active slave asserts an ACK on the data line only
if the address is valid (NACK if not).
6) The master sends the 8-bit data byte.
7) The slave asserts an ACK on the data line.
8) The master generates a STOP condition.
Burst Write
With this operation the master sends an address and
multiple data bytes to the slave device (Figure 19). The
burst write procedure is as follows:
1) The master sends a START condition.
Figure 17. I
2
C START, STOP, and Repeated START Conditions
Table 5. I
2
C Address Map
SCL
SDA
S Sr P
DIN/A1 CS/A0
READ/
WRITE
I
2
C ADDRESS
0 0
W 0x58
R 0x59
0 1
W 0x5A
R 0x5B
1 0
W 0x5C
R 0x5D
1 1
W 0x5E
R 0x5F