Datasheet
SPI/I
2
C UART with 128-Word FIFOs
MAX3107
44 Maxim Integrated
Serial Controller Interface
The MAX3107 can be controlled through SPI or I
2
C as
defined by the logic on I2C/SPI. See the Pin Configurations
for further details.
SPI Interface
The SPI supports both single-cycle and burst-read/write
access. The SPI master must generate clock and data
signals in SPI MODE0 (i.e., with clock polarity CPOL = 0
and clock phase CPHA = 0).
SPI Single-Cycle Access
Figure 15 shows a single-cycle read and Figure 16
shows a single-cycle write.
SPI Burst Access
Burst access allows writing and reading in one block by
only defining the initial register address in the SPI com-
mand byte. Multiple characters can be loaded into the
transmit FIFO by using the THR (0x00) as the initial burst
read address. Similarly, multiple characters can be read
out of the receiver FIFO by using the RHR (0x00) as the
SPI’s burst read address. If the SPI burst address is dif-
ferent to 0x00, the MAX3107 automatically increments
the register address after each SPI data byte. Efficient
programming of multiple consecutive registers is thus
possible. Chip select, CS/A0, must be kept low during
the whole cycle. The SCLK/SCL clock continues clocking
throughout the burst access cycle. The burst cycle ends
when the SPI master pulls CS/A0 high.
For example, writing 128 bytes into the TxFIFO can be
achieved by a burst write access through the following
sequence:
• Pull CS/A0 low
• Send SPI write command
• Send 128 byes
• Release CS/A0
This takes a total of (1 + 128) x 8 clock cycles.
I
2
C Interface
The MAX3107 contains an I
2
C-compatible interface for
data communication with a host processor (SCL and
SDA). The interface supports a clock frequency up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
Figure 15. SPI Single-Cycle Read
Figure 16. SPI Single-Cycle Write
CS
R A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
SCLK
SDI
SDO
A_ = REGISTER ADDRESS
D_ = 8-BIT REGISTER CONTENTS
CS
W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
SDI
A_ = REGISTER ADDRESS
D_ = 8-BIT REGISTER CONTENTS