Datasheet

SPI/I

C UART with 128-Word FIFOs

MAX3107

43Maxim Integrated

Bit 7: CLKtoRTS

Set the CLKtoRTS bit to 1 to route the baud-rate generator (16x baud rate) output clock to RTS/CLKOUT. The clock

frequency is a factor of 16x, 8x, or 4x of the baud rate, depending on the BRGConfig[5:4] settings.

Bits 6 and 5: No Function

Bit 4: ClockEn

Set the ClockEn bit high to enable an external clocking (crystal or clock generator at XIN). Set the ClockEn bit to 0 to

disable clocking.

Bit 3: PLLBypass

Set the PLLBypass bit high to enable bypassing the internal PLL and predivider.

Bit 2: PLLEn

Set the PLLEn bit high to enable the internal PLL. If PLLEn is set low, the internal PLL is disabled.

Bit 1: CrystalEn

Set the CrystalEn bit high to enable the crystal oscillator. When using an external clock source at XIN, CrystalEn must

be set low.

Bit 0: No Function

Always keep Bit 0 at logic 0.

Bit 7–0: Bit[7:0]

The RevID register indicates the revision number of the MAX3107 silicon, starting with 0xA1. This can be used during

software development.

CLKSource—Clock Source Register

RevID—Revision Identification Register

ADDRESS: 0x1E

MODE: R/W

BIT 7 6 5 4 3 2 1 0

NAME

CLKtoRTS — — ClockEn PLLBypass PLLEn CrystalEn —

RESET

0 0 0 0 1 0 0 0

ADDRESS: 0x1F

MODE: R

BIT 7 6 5 4 3 2 1 0

NAME

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

RESET

1 0 1 0 0 0 0 1