Datasheet
Table 5. Bit Descriptions (continued)
SPI/MICROWIRE-Compatible
UART in QSOP-16
POR
STATE
DESCRIPTION
READ/
WRITE
BIT
NAME
0SHDNi w
Software-Shutdown Bit. Enter software shutdown with a write configuration where SHDNi = 1.
Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a write configuration where SHDNi = 0. The
oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer
to the
Pin Description
for hardware shutdown (SHDN input).
0SHDNo r
Shutdown Read-Back Bit. The read-configuration register outputs SHDNo = 1 when the UART
is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T =
1). This tells the processor when it may shut down the RS-232 driver. This bit is also set imme-
diately when the device is shut down through the SHDN pin.
0RA/FE r
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-
ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next proper-
ly framed character independent of the FIFO being enabled. When the device wakes up, it is
likely that a framing error will occur. This error can be cleared with a write configuration. The
FE bit is not cleared on a Read Data operation. When an FE is encountered, the UART resets
itself to the state where it is looking for a start bit.
0ST w
Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.
0ST r Reads the value of the ST bit.
0
TM
w
Mask for T bit. IRQ is asserted if TM = 1 and T = 1 (Table 6).
0
TM
r
Reads the value of the TM bit (Table 6).
1T r
Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.
0
TE
w
Transmit-Enable Bit. If TE = 1, then only the RTS pin will be updated on CS’s rising edge. The
contents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE = 0.
IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
PE = 1, L = 1
TIME
D0START D1 D2 D3 D4 D5 D6 Pt
STOPSTOP
IDLE
IDLE
PE = 1, L = 0
D0START D1 D2 D3 D4 D5 D6 D7 Pt STOP STOP IDLE
IDLE
PE = 0, L = 1
D0START D1 D2 D3 D4 D5 D6 STOP STOP IDLE
IDLE
PE = 0, L = 0
D0START D1 D2 D3 D4 D5 D6 D7 STOP STOP IDLE
Figure 5. Parity and Word-Length Control
MAX3100
10
Maxim Integrated
MAX3100