Datasheet

Hot-Swap Line Transient
The circuit of Figure 11 shows a typical offset termina-
tion used to guarantee a greater than 200mV offset
when a line is not driven (the 50pF represents the mini-
mum parasitic capacitance that would exist in a typical
application). During a hot-swap event when the driver
is connected to the line and is powered up, the driver
must not cause the differential signal to drop below
200mV. Figures 12, 13, and 14 show the results of the
MAX3060E during power-up for three different V
CC
ramp rates (0.1V/µs, 1V/µs, and 10V/µs). The photos
show the V
CC
ramp, the single-ended signal on each
side of the 100Ω termination, as well as the differential
signal across the termination.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly. The
MAX3060E family’s receiver inputs/driver outputs (A, B)
have extra protection against static electricity found in
normal operation. Maxim’s engineers developed state-
of-the-art structures to protect these pins against
±15kV ESD without damage. After an ESD event, the
devices continue working without latchup.
ESD protection can be tested in several ways. The
receiver inputs are characterized for protection to the
following:
• ±15kV using the Human Body Model
• ±7kV using the Contact Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
• ±7kV using the Air-Gap Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
MAX3060E/MAX3061E/MAX3062E
±15kV ESD-Protected, Fail-Safe, 20Mbps, Slew-Rate-
Limited RS-485/RS-422 Transceivers in a SOT
______________________________________________________________________________________ 13
MAX3060E/MAX3061E/MAX3062E
DI
5.0V
V
CC
0.1kΩ
1kΩ
1kΩ
V
CC
OR GND
A
B
50pF
Figure 11. Typical Offset Termination
40μs/div
5V
238mV
20mV/div
200mV/div
0
200mV/div
B
V
CC
A
A - B
Figure 12. Differential Power-Up Glitch (0.1V/µs)
2μs/div
B
V
CC
238mV
20mV/div
5V
A
A - B
20mV/div
20mV/div
0
Figure 13. Differential Power-Up Glitch (1V/µs)
200ns/div
B
V
CC
238mV
20mV/div
5V
A
A - B
50mV/div
50mV/div
0
Figure 14. Differential Power-Up Glitch (10V/µs)