Datasheet

MAX3060E/MAX3061E/MAX3062E
±15kV ESD-Protected, Fail-Safe, 20Mbps, Slew-Rate-
Limited RS-485/RS-422 Transceivers in a SOT
12 ______________________________________________________________________________________
Hot-Swap Capability
Hot-Swap Input
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus can
lead to data errors. Upon initial circuit board insertion, the
data communication processor undergoes its own power-
up sequence. During this period, the processor’s logic-
output drivers are high impedance and are unable to
drive the DE and RE inputs of the MAX306_E to a defined
logic level. Leakage currents up to ±10µA from the high-
impedance state of the processor’s logic drivers could
cause standard CMOS enable inputs of a transceiver to
drift to an incorrect logic level. Additionally, parasitic cir-
cuit board capacitance could cause coupling of V
CC
or
GND to the enable inputs. Without the hot-swap capabili-
ty, these factors could improperly enable the transceiver’s
driver or receiver.
When V
CC
rises, an internal pulldown circuit holds DE
low for at least 10µs and until the current into DE
exceeds 200µA. After the initial positive transition, the
pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
Hot-Swap Input Circuitry
These devices’ enable inputs feature hot-swap capabili-
ty. At the input there are two NMOS devices, M1 and M2
(Figure 10). When V
CC
ramps from zero, an internal 10µs
timer turns on M2 and sets the SR latch, which also turns
on M1. Transistors M2, a 300µA current sink, and M1, a
30µA current sink, pull DE to GND through an 8kΩ resis-
tor. M2 is designed to pull DE to the disabled state
against an external parasitic capacitance up to 100pF
that can drive DE high. After 10µs, the timer deactivates
M2 while M1 remains on, holding DE low against three-
state leakages that can drive DE high. M1 remains on
until an external source overcomes the required input
current. At this time, the SR latch resets and M1 turns off.
When M1 turns off, DE reverts to a standard, high-
impedance CMOS input. Whenever V
CC
drops below
1V, the hot-swap input is reset.
For RE, there is a complementary circuit employing two
PMOS devices pulling RE to V
CC
.
Functional Tables
Table 1. Transmitter Functional Table
Table 2. Receiver Functional Table
X = Don’t care.
*Shutdown mode, driver and receiver outputs are high impedance.
TRANSMITTING
INPUTS OUTPUTS
RE DE DI B A
X1101
X1010
0 0 X High-Z High-Z
1 0 X Shutdown*
RECEIVING
INPUTS OUTPUT
RE DE A-B
RO
0X≥ -0.05V
1
0X≤ -0.2V
0
0 X Open/shorted
1
1 1 X High-Z
1 0 X Shutdown
V
CC
TIMER
TIMER
DE
DE
(HOT SWAP)
10μs
30μA
M1 M2
8kΩ
300μA
SR LATCH
Figure 10. Simplified Structure of the Driver Enable Input (DE)