Datasheet

error on its respective poles, while the same mismatch in a
ladder filter design will spread its error over all poles.
The MAX291/MAX292/MAX295/MAX296 input impedance
is effectively that of a switched-capacitor resistor (see
equation below, and Table 1), and it is inversely proportion-
al to frequency. The input impedance values determined
below represent average input impedance, since the input
current is not continuous. The input current flows in a series
of pulses that charge the input capacitor every time the
appropriate switch is closed. A good rule of thumb is that
the driver’s input source resistance should be less than
10% of the filter’s input impedance. The input impedance
of the filter can be estimated using the following formula:
Z = 1 / (f
CLK
* C)
where: f
CLK
= Clock Frequency
The input impedance for various clock frequencies is
given below:
Clock-Signal Requirements
The MAX291/MAX292/MAX295/MAX296 maximum rec-
ommended clock frequency is 2.5MHz, producing a cutoff
frequency of 25kHz for the MAX291/MAX292 and 50kHz
for the MAX295/MAX296. The CLK pin can be driven by
an external clock or by the internal oscillator with an exter-
nal capacitor. For external clock applications, the clock
circuitry has been designed to interface with +5V CMOS
logic. Drive the CLK pin with a CMOS gate powered from
0V and +5V when using either a single +5V supply or dual
+5V supplies. The MAX291/MAX292/MAX295/MAX296
supply current increases slightly (<3%) with increasing
clock frequency over the clock range 100kHz to 1MHz.
Varying the rate of an external clock will dynamically ad-
just the corner frequency of the filter.
Ideally, the MAX291/MAX292/MAX295/MAX296 should
be clocked symmetrically (50% duty cycle). MAX291/
MAX292/MAX295/MAX296 can be operated with clock
asymmetry of up to 60/40% (or 40/60%) if the clock
remains HIGH and LOW for at least 200ns. For example,
if the part has a maximum clock rate of 2.5MHz, then the
clock should be high for at least 200ns, and low for at
least 200ns.
When using the internal oscillator, the capacitance (C
OSC
)
from CLK to ground determines the oscillator frequency:
The stray capacitance at CLK should be minimized be-
cause it will affect the internal oscillator frequency.
___________Application Information
Power Supplies
The MAX291/MAX292/MAX295/MAX296 operate from
either dual or single power supplies. The dual-supply volt-
age range is +2.375V to +5.500V. The ±2.5V dual supply is
equivalent to single-supply operation (Figure 3). Minor per-
formance degradation could occur due to the external
resistor divider network, where the GND pin is biased to
mid-supply.
Input Signal Range
The ideal input signal range is determined by observing at
what voltage level the total harmonic distortion plus noise
(THD + Noise) ratio is maximized for a given corner fre-
quency. The Typical Operating Characteristics show the
MAX291/MAX292/MAX295/MAX296 THD + Noise response
as the input signal’s peak-to-peak amplitude is varied.
Uncommitted Op Amp
The uncommitted op amp has its noninverting input tied
to the GND pin, and can be used to build a 1st- or 2nd-
f kHz
CpF
OSC
OSC
()
()
≈
10
3
5
8th-Order, Lowpass,
Switched-Capacitor Filters
C2
R1 L1 L3 L5 L7
V
IN
C4 C6 C8 R2
V
O
Figure 2. 8th-Order Ladder Filter Network
MAX29_
CLK
1
+1V TO +4V
INPUT SIGNAL
RANGE
5
+5V
OUTPUT
0V
6
3
4
+5V
0V
8
OUT
GND
V-
V+
7
2
OP OUT
OP IN-
IN
0.1µF
10k
10k 0.1µF
Figure 3. +5V Single-Supply Operation
Table 1. Input Impedance for Various Clock
Frequencies
1000kHz
(kΩ)
446
305
224
237
100kHz
(MΩ)
4.46
3.05
2.24
2.37
10kHz
(MΩ)
44.6
30.5
22.4
23.7
C (pF)
MAX291 2.24
MAX292 3.28
PART
MAX295 4.47
MAX296 4.22
Pin Configuration is 8-pin DIP.
MAX291/MAX292/MAX295/MAX296
Maxim Integrated
7