Datasheet

MAX2831/MAX2832

2.4GHz to 2.5GHz 802.11g/b

RF Transceivers with Integrated PA

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Table 20. Register 5 (A3:A0 = 0101)

BIT RECOMMENDED DESCRIPTION

D13:D10 0000 Set to recommended value.

D9 0

Lock-Detect Output Internal Pullup Resistor Enable. Set to 1 to enable internal 30kΩ pullup

resistor or set to 0 to disable the resistor. Only available when lock-detect, open-drain output

is selected (A3:A0 = 0010, D12 = 1).

D8:D6 010 Set to recommended value.

D5 1

Lock-Detect Output Enable. Set to 1 to enable the lock-detect output or set to 0 to disable the

output. The output is high impedance when disabled.

D4:D3 00 Set to recommended value.

D2 1 Reference Frequency Divider Ratio to PLL. Set to 0 to divide by 1. Set to 1 to divide by 2.

D1:D0 00 Set to recommended value.

Table 15. Register 0 (A3:A0 = 0000)

DATA BITS RECOMMENDED DESCRIPTION

D13:D11 000 Set to recommended value.

D10 1

Fractional-N PLL Mode Enable. Set 1 to enable the fractional-N PLL or set 0 to enable the

integer-N PLL.

D9:D0 1101000000 Set to recommended value.

Table 16. Register 1 (A3:A0 = 0001)

DATA BITS RECOMMENDED DESCRIPTION

D13 0 Set to recommended value.

D12 1

Lock-Detector Output Select. Set to 1 for CMOS Output. Set to 0 for open-drain output. Bit D9

in register (A3:A0 = 0101) enables or disables an internal 30kΩ pullup resistor in open-drain

output mode.

D11:D0 000110011010 Set to recommended value.

Table 17. Register 2 (A3:A0 = 0010)

DATA BITS RECOMMENDED DESCRIPTION

D13:D0 01000000000011 Set to recommended value.

This register contains the 8-bit integer portion and 6 LSBs of the fractional portion of the divider ratio of the synthesizer.

Table 18. Register 3 (A3:A0 = 0011)

BIT RECOMMENDED DESCRIPTION

D13:D8 00000 6 LSBs of 20-Bit Fractional Portion of Main Divider

D7:D0 01111001 8-Bit Integer Portion of Main Divider. Programmable from 64 to 255.

Table 19. Register 4 (A3:A0 = 0100)

BIT RECOMMENDED DESCRIPTION

D13:D0 11011001100110 14 MSBs of 20-Bit Fractional Portion of Main Divider