Datasheet

MAX2831/MAX2832
2.4GHz to 2.5GHz 802.11g/b
RF Transceivers with Integrated PA
24 ______________________________________________________________________________________
Transmitter Variable-Gain Amplifier
The variable-gain amplifier of the transmitter provides
31dB of gain control range programmable in 0.5dB
steps over the top 8dB of the gain control range and in
1dB steps below that. The transmitter gain can be pro-
grammed serially through the SPI interface by setting
bits D5:D0 in Register 12 (A3:A0 = 1100) or in parallel
through the digital logic gain-control pins B6:B1 (pins
3, 6, 8, 11, 14, 23, and 34, respectively). Set bit D10 =
0 in Register 9 (A3:A0 = 1001) to enable parallel pro-
gramming, and set bit D10 = 1 to enable programming
through the 3-wire serial interface. See Table 10 for the
transmitter VGA gain-control settings.
Power-Amplifier Driver Output Matching (MAX2832)
The PA driver of the MAX2832 has a 100Ω differential
output with on-chip AC-coupling capacitors. Provide
electrically symmetrical traces to present a balanced
load to the PA driver output to help maintain driver lin-
earity and RF common-mode rejection.
Power-Amplifier Bias, Enable Delay
and Output Matching (MAX2831)
The MAX2831 integrates a 2-stage PA, providing
+18.5dBm of output power at 5.6% EVM (54Mbps
OFDM signal) in 802.11g mode while exceeding the
802.11g spectral mask requirements. The first and sec-
ond stage PA bias currents are set through program-
ming bits D2:D0 and bits D6:D3 in Register 10 (A3:A0 =
1010), respectively. An adjustable PA enable delay, rel-
ative to the transmitter enable (RXTX low-to-high transi-
tion), can be set from 200ns to 7µs through
programming bits D13:D10 in Register 10 (A3:A0 =
1010).
The PA of the MAX2831 has a 100Ω differential output
that is internally matched. The output has to be AC-cou-
pled using two off-chip 1.5pF capacitors to a 100Ω:50Ω
balun. Provide electrically symmetrical traces from the
PA output to the balun to present a balanced load and to
reduce out-of-band spurs.
Power Detector (MAX2831)
The MAX2831 integrates a voltage-peak detector at the
PA output and provides an analog voltage proportional
to PA output power. See the Power Detector Over
Frequency and Power Detector Over Supply Voltage
graphs in the Typical Operating Characteristics. Set bits
D9:D8 = 10 in Register 8 (A3:A0 = 1000) to multiplex the
power-detector analog output voltage to the RSSI output
(pin 16).
Synthesizer Programming
The MAX2831/MAX2832 integrate a 20-bit sigma-delta
fractional-N synthesizer, allowing the device to achieve
excellent phase-noise performance (0.9° RMS from
10kHz to 10MHz), fast PLL settling times, and an RF fre-
quency step-size of 20Hz. The synthesizer includes a
divide-by-1 or a divide-by-2 reference frequency
divider, an 8-bit integer portion main divider with a divi-
sor range programmable from 64 to 255, and a 20-bit
fractional portion main-divider. Bit D2 in Register 5
(A3:A0 = 0101) sets the reference oscillator divider ratio
to 1 or 2. Bits D7:D0 in Register 3 (A3:A0 = 0011) set
the integer portion of the main divider. The 20-bit frac-
tional portion of the main-divider is split between two
registers. The 14 MSBs of the fractional portion are set
in Register 4 (A3:A0 = 0100), and the 6 LSBs of the frac-
tional portion of the main divider are set in Register 3
(A3:A0 = 0011). See Tables 11 and 12.
Table 10. Transmitter VGA Gain-Control
Settings
NUMBER
D5:D0 Or
B6:B1
OUTPUT SIGNAL POWER
63 111111 Max
62 111110 Max - 0.5dB
61 111101 Max - 1.0dB
:: :
49 110001 Max - 7dB
48 110000 Max - 7.5dB
47 101111 Max - 8dB
46 101110 Max - 8dB
45 101101 Max - 9dB
44 101100 Max - 9dB
:: :
5 000101 Max - 29dB
4 000100 Max - 29dB
3 000011 Max - 30dB
2 000010 Max - 30dB
1 000001 Max - 31dB
0 000000 Max - 31dB