Datasheet

MAX2831/MAX2832
2.4GHz to 2.5GHz 802.11g/b
RF Transceivers with Integrated PA
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Detailed Description
The MAX2831/MAX2832 single-chip, low-power, direct
conversion, zero-IF transceivers are designed to support
802.11g/b applications operating in the 2.4GHz to
2.5GHz band. The fully integrated transceivers include a
receive path, transmit path, voltage-controlled oscillator
(VCO), sigma-delta fractional-N synthesizer, crystal oscil-
lator, RSSI, PA power detector (MAX2831), temperature
sensor, Rx and Tx I/Q error-detection circuitry, baseband-
control interface and linear power amplifier (MAX2831).
The only additional components required to implement a
complete radio front-end solution are a crystal, a pair of
baluns, a BPF, a switch, and a small number of passive
components (RCs, no inductors required).
Receiver
The fully integrated receiver achieves a noise figure of
2.6dB in high-gain mode, and an input compression point
of -6dBm in low-gain mode, while consuming only 62mA
of supply current. The receiver integrates an LNA and
VGA with a 95dB digitally programmable gain control
range, direct-conversion downconverters, I/Q baseband
lowpass filters with programmable LPF corner frequen-
cies, analog RSSI and integrated DC-offset correction cir-
cuitry. A logic-low on the RXTX input (pin 48) and a
logic-high on the SHDN input (pin 12) enable the receiver.
LNA Input Matching
The LNA features a differential input that is internally
AC-coupled and internally matched to 100Ω. Connect a
2:1 balun transformer directly to the RXRF+ (pin 4) and
RXRF- (pin 5) ports to convert the differential 100Ω
input impedance to a single-ended 50Ω input. Provide
electrically symmetrical input traces from the LNA input
to the balun to maintain IP2 performance and RF com-
mon-mode noise rejection.
LNA Gain Control
The LNA has three gain modes: max gain, max gain -
16dB, and max gain - 33dB. The three LNA gain modes
can be serially programmed through the SPI™ interface
by programming bits D6:D5 in Register 11 (A3:A0 =
1011) or programmed in parallel through the digital
logic gain-control pins, B7 (pin 6) and B6 (pin 3). Set
bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable pro-
gramming through the SPI interface, or set bit D12 = 0
to enable parallel programming. See Table 1 for LNA
gain-control settings.
Pin Description (continued)
PIN NAME FUNCTION
35 RXBBQ-
36 RXBBQ+
Receiver Baseband Q-Channel Differential Outputs. In TX calibration mode, these pins are the LO
leakage and sideband detector outputs.
37 RXBBI-
38 RXBBI+
Receiver Baseband I-Channel Differential Outputs. In TX calibration mode, these pins are the LO
leakage and sideband detector outputs.
39 V
CCRXVGA
Receiver VGA Supply Voltage
40 RXHP Receiver Baseband AC-Coupling High-Pass Corner Frequency Control Logic Input
41 V
CCRXFL
Receiver Baseband Filter Supply Voltage
42 TXBBQ-
43 TXBBQ+
Transmitter Baseband I-Channel Differential Inputs
44 TXBBI-
45 TXBBI+
Transmitter Baseband Q-Channel Differential Inputs
46 V
CCRXMX
Receiver Downconverters Supply Voltage
47 GNDTEST Connect to Ground
48 RXTX RX/TX Mode Control Logic Input. See Table 31 for operating modes.
—EP
Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat
dissipation. Do not share with any other pin grounds and bypass capacitors' ground.
Table 1. LNA Gain-Control Settings (Pins
B7:B6 or Register A3:A0 = 1011, D6:D5)
B7 OR D6 B6 OR D5 NAME DESCRIPTION
1 1 High Max gain
1 0 Medium Max gain - 16dB (typ)
0 X Low Max gain - 33dB (typ)
SPI is a trademark of Motorola, Inc.