Datasheet

MAX2831/MAX2832
2.4GHz to 2.5GHz 802.11g/b
RF Transceivers with Integrated PA
20 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1V
CCLNA
LNA Supply Voltage
2 GNDRXLNA LNA Ground
3 B6 Receiver and Transmitter Gain-Control Logic-Input Bit 6
4 RXRF+
5 RXRF-
LNA Differential Input. Input is internally AC-coupled and matched to 100Ω differential. Connect
directly to a 2:1 balun.
6 B7 Receiver Gain-Control Logic-Input Bit 7
7V
CCPA
Supply Voltage for Second Stage of Power Amplifier
8 B3 Receiver and Transmitter Gain-Control Logic-Input Bit 3
9 TXRF+
10 TXRF-
Power-Amplifier Differential Output for the MAX2831. PA output must be AC-coupled. PA driver
internally AC-coupled differential outputs and matched to 100Ω differential for the MAX2832. Connect
directly to a 2:1 balun.
11 B2 Receiver and Transmitter Gain-Control Logic-Input Bit 2
12 SHDN Active-Low Shutdown and Standby Logic Input. See Table 31 for operating modes.
13 V
CCTXPA
Supply Voltage for First-Stage of PA and PA Driver
14 B5 Receiver and Transmitter Gain-Control Logic-Input Bit 5
15 CS Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (See Figure 2)
16 RSSI RSSI, PA Power Detector (MAX2831 Only) or Temperature-Sensor Multiplexed Analog Output
17 V
CCTXMX
Transmitter Upconverter Supply Voltage
18 SCLK Serial-Clock Logic Input of 3-Wire Serial Interface (See Figure 2)
19 DIN Data Logic Input of 3-Wire Serial Interface (See Figure 2)
20 V
CCPLL
PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings.
21 CLOCKOUT Reference Clock Buffer Output
22 LD
Lock- D etect Log i c Outp ut of Fr eq uency S ynthesi zer . O utp ut hi g h i nd i cates that the fr eq uency synthesi zer
i s l ocked . O utp ut p r og r am m ab l e as C M OS or op en- d r ai n outp ut. ( S ee Tab l es 16 and 20.)
23 B1 Receiver and Transmitter Gain-Control Logic-Input Bit 1
24 CPOUT
Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT and TUNE
(see the Block Diagrams/Typical Operating Circuits).
25 V
CCCP
PLL Charge-Pump Supply Voltage
26 GNDCP Charge-Pump Circuit Ground
27 V
CCXTAL
Crystal Oscillator Supply Voltage
28 XTAL Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.
29 CTUNE
Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input,
leave CTUNE unconnected.
30 V
CCVCO
VCO Supply Voltage
31 GNDVCO VCO Ground
32 TUNE VCO TUNE Input (see the Block Diagrams/Typical Operating Circuits)
33 BYPASS
On-Chip VCO Regulator Output Bypass. Bypass with a 0.1µF to 1µF capacitor to GND. Do not
connect other circuitry to this point.
34 B4 Receiver and Transmitter Gain-Control Logic-Input Bit 4