Datasheet
2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA,
and Rx/Tx/Antenna Diversity Switch
Crystal Oscillator
The crystal oscillator has been optimized to work with
low-cost crystals (e.g., Kyocera CX-3225SB). See
Figure 2. The crystal oscillator frequency can be fine
tuned through bits D6:D0 in Register 14 (A3:A0 = 1110),
which control the value of C
TUNE
from 0.5pF to 15.4pF in
0.12pF steps. See the Crystal-Oscillator Offset
Frequency vs. Crystal-Oscillator Tuning Bits graph in the
Typical Operating Characteristics
. The crystal oscillator
can be used as a buffer for an external reference fre-
quency source. In this case, the reference signal is AC-
coupled to the XTAL pin, and capacitors C1 and C2 are
not connected. When used as a buffer, the XTAL input
pin has to be AC-coupled. The XTAL pin has an input
impedance of 5kΩ || 4pF, (set D6:D0 = 0000000 in
Register 14 A3:A0 = 1110).
Reference Clock Output Divider/Buffer
The reference oscillator of the MAX2830 has a divider
and a buffered output for routing the reference clock to
the accompanying baseband IC. Bit D10 in Register 14
(A3:A0 = 1110) sets the buffer divider to divide by 1 or
2, independent of the divide ratio for the reference fre-
quency provided to the PLL. Bit B9 in the same register
enables or disables the reference buffer output. See
the Clock Output waveform in the
Typical Operating
Characteristics
.
Loop Filter
The PLL charge-pump output, CPOUT (pin 24), con-
nects to an external third-order, lowpass RC loop-filter,
which in turn connects to the voltage tuning input,
TUNE (pin 32), of the VCO, completing the PLL loop.
The charge-pump output sink and source current is
1mA, and the VCO tuning gain is 103MHz/V at 0.5V
tune voltage and 86MHz/V at 2.2V tune voltage. The RC
loop-filter values have been optimized for a loop band-
width of 150kHz, to achieve the desired Rx/Tx turn-
around settling time, while maintaining loop stability
and good phase noise. Refer to the MAX2830 EV kit
schematic for the recommended loop-filter component
values. Keep the line from this pin to the tune input as
short as possible to prevent spurious pickup.
Lock-Detector Output
The PLL features a logic lock-detect output. A logic-high
indicates the PLL is locked, and a logic-low indicates
the PLL is not locked. Bit D5 in Register 5 (A3:A0 =
0101) enables or disables the lock-detect output. Bit
Figure 2. Crystal Oscillator Schematic
XTAL
CTUNE
5.9kΩ
C
TUNE
C2
C1
FOR EXTERNAL REFERENCE CLOCK SET, C1 = C2 = OPEN
1.35kΩ
28
29
MAX2830
Table 14. IEEE 802.11g/b Divider-Ratio Programming Words
INTEGER DIVIDER FRACTIONAL DIVIDER
f
RF
(MHz)
(f
RF
/ f
COMP
)
A3:A0 = 0011, D7:D0 A3:A0 = 0100, D13:D0 A3:A0 = 0011, D13:D8
2412 120.6 0111 1000b 2666h 1Ah
2417 120.85 0111 1000b 3666h 1Ah
2422 121.1 0111 1001b 0666h 1Ah
2427 121.35 0111 1001b 1666h 1Ah
2432 121.6 0111 1001b 2666h 1Ah
2437 121.85 0111 1001b 3666h 1Ah
2442 122.1 0111 1010b 0666h 1Ah
2447 122.35 0111 1010b 1666h 1Ah
2452 122.6 0111 1010b 2666h 1Ah
2457 122.85 0111 1010b 3666h 1Ah
2462 123.1 0111 1011b 0666h 1Ah
2467 123.35 0111 1011b 1666h 1Ah
2472 123.6 0111 1011b 2666h 1Ah
2484 124.2 0111 1100b 0CCCh 33h
Maxim Integrated
25
MAX2830