Datasheet

MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 21
mode 1 the maximum signal is 0 times the input signal,
the input should not exceed ±(2/Q)V, or ±1V in this case.
Clock Feedthrough and Noise
Typical wideband noise for MAX260 series devices is
0.5mV
P-P
from DC to 100kHz. The noise is virtually
independent of clock frequency. In multistage filters,
the section with the highest Q should be placed first for
lower output noise.
The output waveform of the MAX260 series and other
switched capacitor filters appears as a sampled signal
with stepping or “staircasing” of the output waveform
occurring at the internal sample rate (f
CLK
/2). This step-
ping, if objectionable, can be removed by adding a sin-
gle-pole AC filter. With no input signal, clock-related
feedthrough is approximately 8mV
P-P
. This can also be
attenuated with an RC-smoothing filter as shown with
the MAX261 in Figure 17.
Some noise also can be generated at the filter outputs
by transitions at the logic inputs. If this is objectionable,
the digital lines should be buffered from the device by
logic gates as shown in Figure 6.
Input Impedance
The input to each filter is the switched capacitor circuit
shown in Figure 18. In the MAX260, the input capacitor
charges to the input voltage V
IN
during the first half
clock cycle. During the second half-cycle, its charge is
transferred to the feedback capacitor. The resultant
input impedance can be approximated by:
R
IN
= 1 / (C
IN
f
CLK
/ 2) = 2 / (C
IN
f
CLK
).
C
IN
is around 12pF, hence, for a clock frequency of
500kHz, R
IN
= 333kΩ. The input also has about 5pF of
fixed capacitance to ground.
The MAX261/MAX262 input structure is shown in Figure
19. Here C
A
= 12pF and C
B
= 0.016pF and only C
B
is
switched, so the input resistance is 750 times larger
compared to the MAX260 (R
IN
= 250MΩ). The
MAX261/MAX262 have a fixed capacitance of approxi-
mately 5pF to ground.
f
0
and Q at Low Sample Rates
When low f
CLK
/f
0
ratios and low Q settings are select-
ed, deviation from ideal continuous filter response can
be noticeable in some designs. This is due to interac-
tion between Q and f
0
at low f
CLK
/f
0
ratios and Qs. The
data in Figure 20 quantifies these differences. Since the
MAX260
MAX261
MAX262
WR
A0–A3
D0, D1
IN
A
OR
IN
B
CMOS
LOGIC
LEVELS
V
+
V
-
GND
0.1µF
0.1µF
+5V
4.7µF
4.7kΩ
4.7kΩ
NOTE: OP-AMP LEVEL SHIFT CIRCUIT HAS A GAIN OF 0.5 FROM V*.
V
IN
V
IN
TO V+
TO GND PIN
2.5kΩ
7.5kΩ
10kΩ
10kΩ
+
-
SEE
NOTE
V
IN
4.7µF
5V
0V
5V
0V
ANY DC
0V
Figure 16. Power Supply and Input Connections for Single Supply Operation