Datasheet

MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
10 ______________________________________________________________________________________
PART Q MODE f
CLK
f
0
1 1 1Hz400kHz 0.01Hz4.0kHz
1 2 1Hz425kHz 0.01Hz6.0kHz
1 3 1Hz500kHz 0.01Hz5.0kHz
1 4 1Hz400kHz 0.01Hz4.0kHz
8 1 1Hz500kHz 0.01Hz5.0kHz
8 2 1Hz700kHz
0.01Hz10.0kH
8 3 1Hz700kHz 0.01Hz5.0kHz
8 4 1Hz600kHz 0.01Hz4.0kHz
64 1 1Hz750kHz 0.01Hz7.5kHz
90 2 1Hz500kHz 0.01Hz7.0kHz
64 3 1Hz400kHz 0.01Hz4.0kHz
MAX260
64 4 1Hz750kHz 0.01Hz7.5kHz
1 1 40Hz4.0MHz 0.4Hz40kHz
1 2 40Hz4.0MHz 0.5Hz57kHz
1 3 40Hz4.0MHz 0.4Hz40kHz
1 4 40Hz4.0MHz 0.4Hz40kHz
8 1 40Hz2.7MHz 0.4Hz27kHz
8 2 40Hz2.1MHz 0.5Hz30kHz
MAX261
PART Q MODE f
CLK
f
0
8 3 40Hz1.7MHz 0.4Hz17kHz
8 4 40Hz2.7MHz 0.4Hz27kHz
64 1 40Hz2.0MHz 0.4Hz20kHz
90 2 40Hz1.2MHz 0.4Hz18kHz
64 3 40Hz1.2MHz 0.4Hz12kHz
MAX261
64 4 40Hz2.0MHz 0.4Hz20kHz
1 1 40Hz4.0MHz 1.0Hz100kHz
1 2 40Hz4.0MHz 1.4Hz140kHz
1 3 40Hz4.0MHz 1.0Hz100kHz
1 4 40Hz4.0MHz 1.0Hz100kHz
8 1 40Hz2.5MHz 1.0Hz60kHz
6 2 40Hz1.4MHz 1.4Hz50kHz
8 3 40Hz1.4MHz 1.0Hz35kHz
8 4 40Hz2.5MHz 1.0Hz60kHz
64 1 40Hz1.5MHz 1.0Hz37kHz
90 2 40Hz0.9MHz 1.4Hz32kHz
64 3 40Hz0.9MHz 1.0Hz22kHz
MAX262
64 4 40Hz1.5MHz 1.0Hz37kHz
Table 1. Typical Clock and Center Frequency Limits
IN
A
LP
A
N/HP/AP
A
BP
A
2 6 7
2 4
A0A3 WR CLK
A
CLK
B
OSC OUT CLK OUT OP OUTOP IND0, D1
MODE
A PROGRAM MEMORY
MODE, f
0
, Q
INTERFACE
LOGIC
÷2
f
0
15
QCK
IN
B
LP
B
N/HP/AP
B
BP
B
2 6 7
MODE
B PROGRAM MEMORY
MODE, f
0
, Q
÷2
f
0
V
+
15
QCK
V
-
GND
+
-
MAX261/MAX262 ONLY
∫∫
Figure 3. MAX260/MAX261/MAX262 Block Diagram