Datasheet

MAX2371/MAX2373
LNAs with Step Attenuator and VGA
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Impedance-Matching Network Layout
The input- and output-matching networks are sensitive to
layout-related parasitic inductions. To minimize parasitic
inductance, keep traces short and place components as
close as possible to the chip. To minimize parasitic
capacitance, minimize the area of the plane.
Chip Information
TRANSISTOR COUNT: 360
AGC
RF_V
CCGND
LNA_OUT
LNA_IN
2.775 V
DC
AGC_BYP
EXPONENTIAL
CONVERTER
AGC
AMP
LNA
RF_ATTN
RF
ATTENUATOR
RF
INPUT MATCH
LNA_V
CC
LNA_I
RSET
1.1kΩ
PRECISION
RX_EN
LNA_E
MAX2371
MAX2373
Typical Operating Circuits
Revision History
Pages changed at Rev 1: 1, 8, 10