Datasheet

MAX2121
Complete Direct-Conversion L-Band Tuner
10
Detailed Description
Register Description
The MAX2121 includes 12 user-programmable registers
and two read-only registers. See Table 1 for register
configurations. The register configuration of Table 1
shows each bit name and the bit usage information for all
registers. Note that all registers must be written after and
no earlier than 100µs after the device is powered up. The
VCO autoselection circuit is triggered by writing to regis-
ter 5. Thus register 5 should be the last register to be
written in order to ensure proper PLL lock.
Table 1. Register Configuration
MSB LSB
DATA BYTE
REG
NUMBER
REGISTER
NAME
READ/
WRITE
REG
ADDRESS
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
1
N-Divider
MSB
Write 0x00
FRAC
1
N[14] N[13] N[12] N[11] N[10] N[9] N[8]
2
N-Divider
LSB
Write 0x01 N[7] N[6] N[5] N[4] N[3] N[2] N[1] N[0]
3
Charge
Pump
Write 0x02
CPMP[1]
0
CPMP[0]
0
CPLIN[1]
0
CPLIN[0]
1
F[19] F[18] F[17] F[16]
4
F-Divider
MSB
Write 0x03 F[15] F[14] F[13] F[12] F[11] F[10] F[9] F[8]
5
F-Divider
LSB
Write 0x04 F[7] F[6] F[5] F[4] F[3] F[2] F[1] F[0]
6
XTAL
Buffer and
Reference
Divider
Write 0x05 XD[2] XD[1] XD[0] R[4] R[3] R[2] R[1] R[0]
7 PLL Write 0x06 D24 CPS ICP X X X X X
8 VCO Write 0x07 VCO[4] VCO[3] VCO[2] VCO[1] VCO[0] VAS ADL ADE
9
Lowpass
Filter
Write 0x08 10010111
10 Control Write 0x09 STBY X
PWDN
0
X BBG[3] BBG[2] BBG[1] BBG[0]
11 Shutdown Write 0x0A X
PLL
0
DIV
0
VCO
0
BB
0
RFMIX
0
RFVGA
0
FE
0
12 Test Write 0x0B
CPTST[2]
0
CPTST[1]
0
CPTST[0]
0
X
TURBO
1
LD
MUX[2]
0
LD
MUX[1]
0
LD
MUX[0]
0
13
Status
Byte-1
Read 0x0C POR VASA VASE LD X X X X
14
Status
Byte-2
Read 0x0D VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
X = Don’t care. 0 = Set to 0 for factory-tested operation. 1 = Set to 1 for factory-tested operation.