Datasheet

Read Cycle
When addressed with a read command, the MAX2112
allows the master to read back a single register, or mul-
tiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX2112 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read (see Table 1 for register addresses). The
slave acknowledges the address. Then, a START condi-
tion is issued by the master, followed by the 7 slave
address bits and a read bit (R/W = 1). The MAX2112
issues an ACK if the slave address byte is successfully
received. The MAX2112 starts sending data MSB first
with each SCL clock cycle. At the 9th clock cycle, the
master can issue an ACK and continue to read succes-
sive registers, or the master can terminate the transmis-
sion by issuing a NACK. The read cycle does not
terminate until the master issues a STOP condition.
Figure 3 illustrates an example in which registers 0
through 2 are read back.
Application Information
The MAX2112 downconverts RF signals in the 925MHz to
2175MHz range directly to the baseband I/Q signals. The
devices are targeted for digital DBS tuner applications.
RF Input
The RF input of the MAX2112 is internally matched to
75Ω. Only a DC-blocking capacitor is needed. See the
Typical Application Circuit .
RF Gain Control
The MAX2112 features a variable-gain low-noise ampli-
fier providing 73dB of RF gain range. The voltage con-
trol (VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB
steps. The VGA gain can be serially programmed
through the SPI interface by setting bits BBG[3:0] in the
Control register.
Baseband Lowpass Filter
The MAX2112 includes a programmable on-chip
7th-order Butterworth filter. The filter -3dB corner fre-
quency can be adjusted from approximately 4MHz to
40MHz by programming the LPF[7:0] register using the
following equation:
LPF[7:0]
dec
= (f
-3dB
- 4MHz)/0.29MHz + 12,
where f
-3dB
is in units of MHz.
Total device supply current depends on the filter BW
setting. See Supply Current vs. Baseband Filter Cutoff
Frequency in the Typical Operating Characteristics for
more information.
DC Offset Cancellation
The DC offset cancellation is required to maintain the
I/Q output dynamic range. Connecting an external
capacitor between IDC+ and IDC- forms a highpass fil-
ter for the I channel and an external capacitor between
QDC+ and QDC- forms a highpass filter for the Q chan-
nel. Keep the value of the external capacitor less than
47nF to form a typical highpass corner of 250Hz.
XTAL Oscillator
The MAX2112 contains an internal reference oscillator,
reference output divider, and output buffer. All that is
required is to connect a crystal through a series 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL
pin). See Table 16 for crystal (XTAL) ESR (equivalent
series resistance) requirements.
VCO Autoselect (VAS)
The MAX2112 includes 24 VCOs. The local oscillator
frequency can be manually selected by programming
the VCO[4:0] bits in the VCO register. The selected VCO
is reported in the Status Byte-2 register (see Table 15).
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
DEVICE
ADDRESS
R / W
1100000
REGISTER
ADDRESS
000000000
S
T
A
R
T
S
T
A
R
T
A
C
K
A
C
K
REG 02
DATA
xxxxxxxx
S
T
O
P
N
A
C
K
REG 00
DATA
xxxxxxxx
A
C
K
REG 01
DATA
xxxxxxxx
A
C
K
A
C
K
DEVICE
ADDRESS
R / W
1100000 1
Figure 3. Example: Receive Data from Read Registers
Table 16. Maximum Crystal ESR
Requirement
ESR
MAX
() XTAL FREQUENCY (MHz)
80 12 < f
XTAL
 14
60 14 < f
XTAL
 30
MAX2112
Maxim Integrated
15