Datasheet

MAX2078
Each mixer can be programmed to 1 of 16 phases;
therefore, 4 bits are required for each channel for pro-
gramming. Each CW channel can be programmed to
an off state by setting bit Di to 1. The power-down
mode (PD) line overrides this soft shutdown.
After the serial shift registers have been programmed,
the CS signal, when going high, loads the phase infor-
mation in the form of 5 bits per channel into the I/Q
phase divider/selectors. This presets the dividers,
selecting the appropriate mixer phasing. See Table 3
for mixer phase configurations.
CW Mixer Output Summation
The outputs from the octal-channel mixer array are
summed internally to produce the total CWD summed
beamformed signal. The octal array produces eight
differential quadrature (Q) outputs and eight differential
in-phase (I) outputs. All quadrature and in-phase out-
puts are summed into single I and Q differential current
outputs (CQ+, CQ-, CI+, CI-).
LO Phase Select
The LO phase dividers can be programmed through
the shift registers to allow for 16 quadrature phases for
a complete CW beamforming solution.
Synchronization
Figure 1 illustrates the serial programming of the eight
individual channels through the serial data port. Note
that the serial data can be daisy-chained from one part
to another, allowing a single data line to be used to pro-
gram multiple chips in the system.
Octal-Channel Ultrasound Front-End
with CW Doppler Mixers
18 ______________________________________________________________________________________
PER CHANNEL MSB LSB SHUTDOWN
PHASE (DEGREE) Di + 4 Di + 3 Di + 2 Di + 1 Di
0 0 0 0 0 0/1
22.5 1 0 0 0 0/1
45 0 1 0 0 0/1
67.5 1 1 0 0 0/1
90 0 0 1 0 0/1
112.5 1 0 1 0 0/1
135 0110 0/1
157.5 1 1 1 0 0/1
180 0001 0/1
202.5 1 0 0 1 0/1
225 0101 0/1
247.5 1 1 0 1 0/1
270 0011 0/1
292.5 1 0 1 1 0/1
315 0111 0/1
337.5 1 1 1 1 0/1
Table 3. Mixer Phase Configurations
CHANNEL 1
DIN
DOUT
CLK
AB
C
DSD
B3 B2 B1 B0B4
CHANNEL 2
AB
C
DSD
B3 B2 B1 B0B4
CHANNEL 3
AB
C
DSD
B3 B2 B1 B0B4
CHANNEL 4
AB
C
DSD
B3 B2 B1 B0B4
D43 D42 D41 D40D44D45D46
CHANNEL 5
AB
C
DSD
B3 B2 B1 B0B4
CHANNEL 6
AB
C
DSD
B3 B2 B1 B0B4
CHANNEL 7
AB
C
DSD
B3 B2 B1 B0B4
CHANNEL 8
AB
C
DSD
B3 B2 B1 B0B4
Figure 1. Data Flow of Serial Shift Register