Datasheet

MAX2067
50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
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Pin Description
PIN NAME DESCRIPTION
1, 16, 19, 22, 24–28,
30, 31, 33–36
GND Ground
2 VREF_SELECT
DAC Reference Voltage Selection Logic Input. Logic 1 = internal DAC reference
voltage, Logic 0 = external DAC reference voltage. Logic input disabled (don’t care)
when VDAC_EN = Logic 0.
3 VDAC_EN
DAC Enable/Disable Logic Input. Logic 0 = disable DAC circuit, Logic 1 = enable
DAC circuit.
4 DATA SPI Data Digital Input
5 CLK SPI Clock Digital Input
6 CS SPI Chip-Select Digital Input
7 VDD_LOGIC
Digital Logic Supply Input. Connect to the digital logic power supply, V
DD
, Bypass
to GND with a 10nF capacitor as close as possible to the pin.
8–15, 23, 29 GND Ground. See the Pin-Compatibility Considerations section.
17 AMP_OUT Driver Amplifier Output (50Ω). See the Typical Application Circuit for details.
18 RSET Driver Amplifier Bias-Setting Input. See the External Bias section.
20 AMP_IN Driver Amplifier Input (50Ω). See the Typical Application Circuit for details.
21 VCC_AMP
Driver Amplifier Supply Voltage Input. Connect to the V
CC
power supply. Bypass to
GND with 1000pF and 10nF capacitors as close as possible to the pin, with the
smaller value capacitor closer to the part.
32 ATTEN_OUT
Analog Attenuator Output. Internally matched to 50Ω. Requires an external DC-
blocking capacitor.
37 ATTEN_IN
Analog Attenuator Input. Internally matched to 50Ω. Requires an external DC-
blocking capacitor.
38 VCC_ANALOG
Analog Bias and Control Supply Voltage Input. Bypass to GND with a 10nF
capacitor as close as possible to the pin.
39 ANALOG_VCTRL Analog Attenuator Voltage-Control Input
40 VREF_IN External DAC Voltage Reference Input
—EP
Exposed Pad. Internally connected to GND. Connect EP to ground for proper RF
performance and enhanced thermal dissipation.