Datasheet

MAX2066
50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
22 ______________________________________________________________________________________
GND
38
D2
13
D0
15
36
GND
D1 GND
14
37
GND GND
16
35
TQFN
EXPOSED PAD ON BOTTOM.
CONNECT EP TO GND.
GND
17
34
GND
33
RSET
AMP_OUT
18
GND
32
GND
19
AMP_IN GND
20
31
D3 GND
12
39
D4 GND
11
40
238
SER/PAR ATTEN_OUT
6
CS GND
25
247
VDD_LOGIC GND
5
CLK GND
26
4
DATA
GND
27
3
GNDGND
28
2
ATTEN_INGND
29
229
STATE_A GND
2110
STATE_B VCC_AMP
1
TOP VIEW
30
GND
GND
+
DRIVER AMP
SPI INTERFACE
DIGITAL
ATTENUATOR
MAX2066
Pin Configuration/Functional Block Diagram
Chip Information
PROCESS: SiGe BiCMOS