Datasheet

MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
______________________________________________________________________________________ 25
VCC_ANALOG
38
D2
13
D0
15
36
GND
D1 ATTEN1_IN
14
37
GND GND
16
35
TQFN
EXPOSED PADDLE ON BOTTOM.
CONNECT EP TO GND.
GND
17
34
GND
33
RSET
AMP_OUT
18
ATTEN1_OUT
32
GND
19
AMP_IN GND
20
31
D3 ANALOG_VCTRL
12
39
D4 VREF_IN
11
40
238
SER/PAR ATTEN2_OUT
6
CS GND
25
247
VDD_LOGIC GND
5
CLK GND
26
4
DATA
GND
27
3
GNDVDAC_EN
28
2
ATTEN2_INVREF_SELECT
29
229
STATE_A GND
2110
STATE_B VCC_AMP
1
TOP VIEW
30
GND
GND
+
ANALOG ATTENUATOR
VREF
DAC
DRIVER AMP
SPI INTERFACE
DIGITAL
ATTENUATOR
Pin Configuration/Functional Block Diagram
Chip Information
PROCESS: SiGe BiCMOS