Datasheet
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
______________________________________________________________________________________ 21
Table 2. SPI Data Format (continued)
FUNCTION BIT DESCRIPTION
D7 Bit 7 (MSB) of on-chip DAC used to program the analog attenuator
D6 Bit 6 of DAC
D5 Bit 5 of DAC
D4 Bit 4 of DAC
D3 Bit 3 of DAC
D2 Bit 2 of DAC
D1 Bit 1 of DAC
On-Chip DAC
D0 (LSB) Bit 0 (LSB) of the on-chip DAC
Attenuator and DAC Operation
The analog attenuator is controlled by an external con-
trol voltage applied at ANALOG_VCTRL (pin 39) or by
the on-chip 8-bit DAC, while the digital attenuator is con-
trolled through the SPI-compatible interface or parallel
bus. The DAC enable/disable logic-input pin
(VDAC_EN), digital attenuator SPI or parallel control
selection logic-input pin (SER/PAR), and the DAC refer-
ence voltage selection logic-input pin (VREF_SELECT)
determine how the attenuators are controlled. The on-
chip DAC can also be enabled or disabled. When the
DAC is enabled, either the on-chip voltage reference or
the external voltage reference can be selected. See
Table 1 for the attenuator and DAC operation truth table.
Digital Attenuator Settings
Using the Parallel Control Bus
To capitalize on its fast 25ns switching capability, the
MAX2065 offers a supplemental 5-bit parallel control
interface. The digital logic attenuator-control pins
(D0–D4) enable the attenuator stages (Table 3).
Direct access to this 5-bit bus enables the user to avoid
any programming delays associated with the SPI
interface. One of the limitations of any SPI bus is the
speed at which commands can be clocked into each
peripheral device. By offering direct access to the 5-bit
parallel interface, the user can quickly shift between
digital attenuator states needed for critical “fast-attack”
automatic gain control (AGC) applications.
“Rapid-Fire” Preprogrammed
Attenuation States
The MAX2065 has an added feature that provides
“rapid fire” gain selection between four prepro-
grammed attenuation steps. As with the supplemental
5-bit bus mentioned above, this “rapid fire” gain selec-
tion allows the user to quickly access any one of four
customized digital attenuation states without incurring
the delays associated with reprogramming the device
through the SPI bus.
The switching speed is comparable to that achieved
using the supplemental 5-bit parallel bus. However, by
employing this specific feature, the digital attenuator
I/O is further reduced by a factor of either 5 or 2.5 (5
control bits vs. 1 or 2, respectively) depending on the
number of states desired.
Table 3. Digital Attenuator Settings (Parallel Control)
INPUT LOGIC = 0 (OR GROUND) LOGIC = 1
D0 Disable 1dB attenuator, or when SPI is default programmer Enable 1dB attenuator
D1 Disable 2dB attenuator, or when SPI is default programmer Enable 2dB attenuator
D2 Disable 4dB attenuator, or when SPI is default programmer Enable 4dB attenuator
D3 Disable 8dB attenuator, or when SPI is default programmer Enable 8dB attenuator
D4 Disable 16dB attenuator, or when SPI is default programmer Enable 16dB attenuator