Datasheet

MAX2039
Exposed Pad RF/Thermal Considerations
The EP of the MAX2039’s 20-pin thin QFN-EP package
provides a low thermal-resistance path to the die. It is
important that the PC board on which the MAX2039 is
mounted be designed to conduct heat from the EP. In
addition, provide the EP with a low-inductance path to
electrical ground. The EP MUST be soldered to a
ground plane on the PC board, either directly or
through an array of plated via holes.
Chip Information
TRANSISTOR COUNT: 1212
PROCESS: SiGe BiCMOS
High-Linearity, 1700MHz to 2200MHz Upconversion/
Downconversion Mixer with LO Buffer/Switch
14 ______________________________________________________________________________________
Typical Application Circuit
20 19
GND IF+ IF- GND GND
7 8 9
10
11
12
V
CC
V
CC
LOBIAS
V
CC
V
CC
LOSEL
LOSEL
INPUT
GND
13
14
15
16 17 18
LO1
GND
GND
LO2
INPUT
V
CC
LO2
6
5
4
3
2
1
GND
GND
TAP
RF
C2C3
V
CC
V
CC
MAX2039
V
CC
C4
C1
C12
LO1
INPUT
C10
C5
C6 C7
R1
C11
T1
4
5
1
3
IF
C8
C9
RF