Datasheet

MAX2016
LF-to-2.5GHz Dual Logarithmic Detector/
Controller for Power, Gain, and VSWR Measurements
10 ______________________________________________________________________________________
Detailed Description
The MAX2016 dual logarithmic amplifier is designed for
a multitude of applications including dual-channel RF
power measurements, AGC control, gain/loss detection,
and VSWR monitoring. This device measures RF signals
ranging from low frequency to 2.5GHz, and operates
from a single 2.7V to 5.25V (using series resistor, R6)
power supply. As with its single-channel counterpart
(MAX2015), the MAX2016 provides unparalleled perfor-
mance with a high 80dB dynamic range at 100MHz and
exceptional accuracy over the extended temperature
and supply voltage ranges.
The MAX2016 uses a pair of logarithmic amplifiers to
detect and compare the power levels of two RF input
signals. The device subtracts one power level from the
other to provide a DC output voltage that is proportional
to the power difference (gain). The MAX2016 can also
measure the return loss/VSWR of an RF signal by moni-
toring the incident and reflected power levels associat-
ed with any given load.
A window detector is easily implemented by using the
on-chip comparators, OR gate, and 2V reference. This
combination of circuitry provides an automatic indica-
tion of when the measured gain is outside a program-
mable range. Alarm monitoring can thus be imple-
mented for detecting high-VSWR states (such as open
or shorted loads).
RF Inputs (RFINA and RFINB)
The MAX2016 has two differential RF inputs. The input
to detector A (RFINA) uses the two input ports RFINA+
and RFINA-, and the input to detector B (RFINB) uses
the two input ports RFINB+ and RFINB-.
Pin Description
PIN NAME FUNCTION
1, 28 FA1, FA2
External Capacitor Input. Connecting a capacitor between FA1 and FA2 sets the highpass cutoff
frequency corner for detector A (see the Input Highpass Filter section).
2, 9, 12, 20 V
CC
Supply Voltage. Bypass with capacitors as specified in the Typical Application Circuit. Place
capacitors as close to each V
CC
as possible (see the Power-Supply Connections section).
3, 4 RFINA+, RFINA- Differential RF Inputs for Detector A. Requires external DC-blocking capacitors.
5, 17 GND Ground. Connect to the PCB ground plane.
6 COUTH High-Comparator Output
7 CSETH Threshold Input on High Comparator
8 COR Comparator OR Logic Output. Output of COUTH ORed with COUTL.
10 SETD Set-Point Input for Gain Detector
11 OUTD
DC Output Voltage Representing P
RFINA
- P
RFINB
. This output provides a DC voltage
proportional to the difference of the input RF powers on RFINA and RFINB.
13, 14 FV2, FV1 Video-Filter Capacitor Inputs for OUTD
15 CSETL Threshold Set Input on Low Comparator
16 COUTL Low-Comparator Output
18, 19 RFINB-, RFINB+ Differential RF Inputs for Detector B. Requires external DC-blocking capacitors.
21, 22 FB1, FB2
External Capacitor Input. Connecting a capacitor between FB1 and FB2 sets the highpass cutoff
frequency corner for detector B (see the Input Highpass Filter section).
23 OUTB
Detector B Output. This output provides a voltage proportional to the log of the input power on
differential inputs RFINB+ and RFINB- (RFINB).
24 SETB Set-Point Input for Detector B
25 REF 2V Reference Output
26 SETA Set-Point Input for Detector A
27 OUTA
Detector A Output. This output provides a voltage proportional to the log of the input power on
differential inputs RFINA+ and RFINA- (RFINA).
EP GND Exposed Paddle. EP must connect to the PCB ground plane.