Datasheet

MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Internal acquisition
3.0 5.0
External reference = 4.096V
After FULLPD or STBYPD
External acquisition (Note 9)
CONDITIONS
Full power-down mode (FULLPD) (Note 7)
5
µs
3.0
t
ACQI
Acquisition Time
LSB
±
1
/
2
PSRR
Power-Supply Rejection Ratio
(Note 8)
3.0
t
ACQE
External CLK
µs
V4.75 5.25V
DD
Supply Voltage
6.0
t
CONV
Conversion Time
Internal CLK, C
CLK
= 100pF 6.0 7.7 10.0
To 0.1mV, REF
bypass capacitor
fully discharged
ms
8
Reference Buffer Settling
60 120
60
Normal mode, bipolar ranges
700 850
Normal mode, unipolar ranges
UNITSMIN TYP MAXSYMBOLPARAMETER
Standby power-down (STBYPD)
mA
18
I
DD
Supply Current
610
µA
Internal reference ±
1
/
2
C
CLK
= 100pF MHz1.25 1.56 2.00f
CLK
Internal Clock Frequency
0.1 2.0f
CLK
External Clock Frequency Range MHz
External CLK
Internal CLK
Power-up (Note 10) µs200
Bandgap Reference
Start-Up Time
External CLK
ksps
100
Throughput Rate
Internal CLK, C
CLK
= 100pF 62
C
REF
= 4.7µF
C
REF
= 33µF
V2.4V
INH
Input High Voltage
V0.8V
INL
Input Low Voltage
V
IN
= 0V or V
DD
µA±10I
IN
Input Leakage Current
(Note 5) pF15C
IN
Input Capacitance
V
DD
= 4.75V, I
SINK
= 1.6mA V0.4V
OL
Output Low Voltage
V
DD
= 4.75V, I
SOURCE
= 1mA VV
DD
- 1V
OH
Output High Voltage
(Note 5) pF15C
OUT
Three-State Output Capacitance
POWER REQUIREMENTS
TIMING
DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)
DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)